Technical Reference Guide

5.5.4 PARALLEL INTERFACE PROGRAMMING

Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime.

5.5.4.1 Parallel Interface Configuration

The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account. Address selection, enabling, and EPP/ECP mode parameters of the parallel interface are affected through the PnP configuration registers of the LPC47B367 I/O controller. Address selection and enabling are automatically done by the BIOS during POST but can also be accomplished with the Setup utility and other software.

The parallel interface configuration registers are listed in the following table:

Table 5–10. Parallel Interface Configuration Registers

Table 5-10.

Parallel Interface Configuration Registers

Index

 

 

Reset

Address

Function

R/W

Value

30h

Activate

R/W

00h

60h

Base Address MSB

R/W

00h

61h

Base Address LSB

R/W

00h

70h

Interrupt Select

R/W

00h

74h

DMA Channel Select

R/W

04h

F0h

Mode Register

R/W

00h

F1h

Mode Register 2

R/W

00h

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