Technical Reference Guide

The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.

Configuration

Space

Header

 

 

 

 

 

 

 

 

 

 

 

Register

31

24

23

16

15

8

7

 

0

Index

 

FCh

 

 

 

 

Device-Specific Area

 

 

 

 

 

 

 

 

 

 

40h

 

 

 

 

 

 

 

 

 

 

 

Min. Lat.

 

Min. GNT

Int. Pin

Int. Line

3Ch

 

 

 

 

 

Reserved

 

 

 

 

38h

 

 

 

 

 

Reserved

 

 

 

 

34h

 

 

Expansion ROM Base Address

 

30h

 

 

Subsystem ID

 

Subsystem Vendor ID

2Ch

 

 

 

 

Card Bus CIS Pointer

 

 

 

28h

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address Registers

 

 

 

10h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIST

 

Hdr. Type

Lat. Timer

Line Size

0Ch

 

 

 

 

Class Code

 

 

Revision ID

08h

 

 

Status

 

 

Command

 

04h

 

 

Device ID

 

 

Vendor ID

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

Register

31

24

23

16

15

8

7

 

0

Index

 

FCh

 

 

 

 

 

Device-Specific Area

 

 

 

 

 

 

 

 

 

 

 

40h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bridge Control

 

Int. Pin

Int. Line

3Ch

 

 

 

Expansion ROM Base Address

 

38h

 

 

 

 

 

 

Reserved

 

 

 

 

34h

I/O Limit Upper 16 Bits

I/O Base Upper 16 Bits

30h

 

 

 

Prefetchable Limit Upper 32 Bits

 

2Ch

 

 

 

Prefetchable Base Upper 32 Bits

 

28h

 

Prefetch. Mem. Limit

Prefetch. Mem. Base

24h

 

 

 

Memory Limit

 

 

Memory Base

 

20h

 

 

 

Secondary Status

I/O Limit

I/O Base

1Ch

2

nd

Lat.Tmr

Sub. Bus #

Sec. Bus #

Pri. Bus #

18h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address Registers

 

 

 

10h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0Ch

 

 

 

BIST

 

Hdr. Type

Lat. Timer

Line Size

 

 

 

 

 

Class Code

 

 

Revision ID

08h

 

 

 

Status

 

 

Command

 

04h

 

 

 

Device ID

 

 

Vendor ID

 

00h

PCI Configuration Space Type 0

 

PCI Configuration Space Type 1

 

Data required by PCI protocol

 

Not required

 

 

Figure 4-3.PCI Configuration Space Mapping

Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on the system board are listed in Table 4-2 (NOTE: only devices that are implemented in these systems are listed).

Compaq D315 and hp d325 Personal Computers 4-5

Featuring the AMD Athlon XP Processor

Second Edition - April 2003

Page 55
Image 55
HP D315 manual PCI Configuration Space Type, Bist