Technical Reference Guide
The register index (CF8h, bits <7..2>) identifies the
Configuration
Space
Header
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31 | 24 | 23 | 16 | 15 | 8 | 7 |
| 0 | Index | ||
| FCh | ||||||||||
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| 40h | ||||
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Min. Lat. |
| Min. GNT | Int. Pin | Int. Line | 3Ch | ||||||
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| 38h | |
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| Reserved |
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| 34h | |
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| Expansion ROM Base Address |
| 30h | |||||||
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| Subsystem ID |
| Subsystem Vendor ID | 2Ch | ||||||
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| Card Bus CIS Pointer |
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| 28h | |||
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| Base Address Registers |
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| BIST |
| Hdr. Type | Lat. Timer | Line Size | 0Ch | ||||
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| Class Code |
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| Revision ID | 08h | |||
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| Status |
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| Command |
| 04h | ||||
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| Device ID |
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| Vendor ID |
| 00h |
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| Register |
31 | 24 | 23 | 16 | 15 | 8 | 7 |
| 0 | Index | |||
| FCh | |||||||||||
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| 40h | ||||
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| Bridge Control |
| Int. Pin | Int. Line | 3Ch | |||||
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| Expansion ROM Base Address |
| 38h | |||||||
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| Reserved |
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| 34h | |
I/O Limit Upper 16 Bits | I/O Base Upper 16 Bits | 30h | ||||||||||
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| Prefetchable Limit Upper 32 Bits |
| 2Ch | |||||||
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| Prefetchable Base Upper 32 Bits |
| 28h | |||||||
| Prefetch. Mem. Limit | Prefetch. Mem. Base | 24h | |||||||||
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| Memory Limit |
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| Memory Base |
| 20h | ||||
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| Secondary Status | I/O Limit | I/O Base | 1Ch | ||||||
2 | nd | Lat.Tmr | Sub. Bus # | Sec. Bus # | Pri. Bus # | 18h | ||||||
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| Base Address Registers |
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| 10h | |||
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| 0Ch |
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| BIST |
| Hdr. Type | Lat. Timer | Line Size | |||||
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| Class Code |
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| Revision ID | 08h | |||
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| Status |
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| Command |
| 04h | ||||
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| Device ID |
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| Vendor ID |
| 00h |
PCI Configuration Space Type 0 |
| PCI Configuration Space Type 1 | |
| Data required by PCI protocol |
| Not required |
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Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on the system board are listed in Table 4-2 (NOTE: only devices that are implemented in these systems are listed).
Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition - April 2003