HP D315 manual Option ROM Mapping, PCI Interrupts, PCI Power Management Support, Pci Sub-Busses

Technical Reference Guide

4.2.3 OPTION ROM MAPPING

During POST, the PCI bus is scanned for devices that contain their own specific firmware in ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3).

4.2.4 PCI INTERRUPTS

Eight interrupt signals (INTA- thru INTD-) are available for use by PCI devices. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. For more information on interrupts including PCI interrupt mapping refer to the “System Resources” section 4.4.

4.2.5 PCI POWER MANAGEMENT SUPPORT

This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI Power Management Enable (PME-) signal is supported by the chipset and allows compliant PCI and AGP peripherals to initiate the power management routine.

4.2.6 PCI SUB-BUSSES

The chipset implements two data busses that are supplementary in operation to the PCI bus:

4.2.6.1Hyper Transfer Link Bus

The NVidia NForce chipset implements a Hyper Transfer Link bus between the IGP and the MCP components. This bus operates at 800 MHz and is transparent to software and not accessible for expansion purposes.

4.2.6.2LPC Bus

The MCP and MCP-2 implements a Low Pin Count (LPC) bus for handling transactions to and from the LPC47B367 Super I/O Controller as well as the BIOS ROM. The LPC bus transfers data a nibble (4 bits) at a time at a 33-MHz and is generally transparent in operation. The only consideration required of the LPC bus is during the configuration of DMA channel modes (see section 4.4.3 “DMA”).

Compaq D315 and hp d325 Personal Computers 4-7

Featuring the AMD Athlon XP Processor

Second Edition - April 2003