Chapter 5 Input/Output Interfaces

Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime.

5.8.5.1 Audio Configuration

The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the MCP. Table 5-21 lists the key PCI configuration registers of the audio subsystem. Table 5–21. AC’97 Audio Controller PCI Configuration Registers

Table 5-21.

AC’97 Audio Controller

PCI Configuration Registers (MCP Device 36Function 0)

PCI

 

Value on

PCI

 

Value

Conf.

 

Reset

Conf.

 

on

Addr.

Register

 

Addr.

Register

Reset

00-01h

Vender ID

10DEh

10 – 13h

Audio Base Addr.

1d

02-03h

Device ID

01B1h

14 – 17h

Audio Bus Mstr. Addr.

1d

04-05h

PCI Command

0200h

18 – 1Bh

Audio Mem. Base Addr.

0s

06-07h

PCI Status

00B0h

34h

Capabilities Pointer

44h

08h

Revision ID

A1h

3Ch

Interrupt Line

00h

09h

Class Code

040100h

3Dh

Interrupt Pin

01h

0Ch

Cache Line Size

00h

3Eh

Minimum Grant

02h

0Dh

Latency Timer

00h

3Fh

Maximum Latency

05h

0Eh

Header Type

80h

44h

Power Management Config.

01h

0Fh

BIST

00h

46h

Power Mgmnt. Capabilities

FE02h

5.8.5.2 Audio Control

The audio subsystem is controlled through a set of indexed registers that physically reside in the audio codec . The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described. The audio codec’s control registers (Table 5-22) are mapped into 64 kilobytes of variable I/O space.

Table 5-22.

AC’97 Audio Codec Control Registers

 

 

Value

 

 

Value

 

 

Value

Offset

On

Offset

On

Offset

On

Addr. / Register

Reset

Addr. / Register

Reset

Addr. / Register

Reset

00h

Reset

0100h

14h

Video Vol.

8808h

28h

Ext. Audio ID.

0001h

02h

Master Vol.

8000h

16h

Aux Vol.

8808h

2Ah

Ext. Audio Ctrl/Sts

0000h

04h

Reserved

--

18h

PCM Out Vol.

8808h

2Ch

PCM DAC SRate

BB80h

06h

Mono Mstr. Vol.

8000h

1Ah

Record Sel.

0000h

32h

PCM ADC SRate

BB80h

08h

Reserved

--

1Ch

Record Gain

8000h

34h

Reserved

--

0Ah

PC Beep Vol.

8000h

1Eh

Reserved

--

72h

Reserved

--

0Ch

Phone In Vol.

8008h

20h

Gen. Purpose

0000h

74h

Serial Config.

7x0xh

0Eh

Mic Vol.

8008h

22h

3D Control

0000h

76h

Misc. Control Bits

0404h

10h

Line In Vol.

8808h

24h

Reserved

--

7Ch

Vender ID1

4144h

12h

CD Vol.

8808h

26h

Pwr Mgnt.

000xh

7Eh

Vender ID2

5340h

5-30Compaq D315 and hp d325 Personal Computers Featuring the AMD Athlon XP Processor

Second Edition – April 2003

Page 112
Image 112
HP D315 manual Audio Configuration, Audio Control, AC’97 Audio Codec Control Registers