HP D315 manual Apic Mode, Maskable Interrupt Priorities and Assignments

Technical Reference Guide

8259 Mode

The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259- equivalent logic. Table 4-5 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first.

Table 4-5.Maskable Interrupt Priorities and Assignments

		Table 4-5.
	Maskable Interrupt Priorities and Assignments
Priority	Signal Label	Source (Typical)
1	IRQ0	Interval timer 1, counter 0
2	IRQ1	Keyboard
3	IRQ8-	Real-time clock
4	IRQ9	Unused
5	IRQ10	PCI devices/slots
6	IRQ11	Audio codec
7	IRQ12	Mouse (PS/2)
8	IRQ13	Coprocessor (math)
9	IRQ14	Primary IDE controller
10	IRQ15	Secondary IDE I/F controller
11	IRQ3	Serial port (COM2)
12	IRQ4	Serial port (COM1)
13	IRQ5	Network interface controller
14	IRQ6	Diskette drive controller
15	IRQ7	Parallel port (LPT1)
--	IRQ2	NOT AVAILABLE (Cascade from interrupt controller 2)

APIC Mode

The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages:

♦Eliminates the processor’s interrupt acknowledge cycle by using a separate (APIC) bus

♦Programmable interrupt priority

♦Additional interrupts (total of 24)

The APIC mode accommodates five PCI interrupt signals (INTA-..INTE-) for use by PCI devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:

MCP		PCI	PCI	PCI	AGP
Int. Cntlr.		Slot 1	Slot 2	Slot 3	Slot
INTA-	Wired	INTA-	INTD-	INTC-	INTB-
INTB-		INTB-	INTA-	INTD-	—
	to
INTC-		INTC-	INTB-	INTA-	—
INTD-		INTD-	INTC-	INTB-	—
INTE-		—	—	—	INTA-
NOTE:

Internal functions of the MCP (USB, MAC, SMBus, Audio, IDE controllers) use INTA-.

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Second Edition - April 2003