NXP Semiconductors LPC2919 user manual LPC2917/19 block diagram, overview of clock areas

Page 12

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT

 

T

DRA

DRA DR

F

F

 

DRAF

DRAFT DRAFT

 

 

 

 

 

 

 

 

 

 

DRAFT DRAFT

 

LPC2917/19

 

ITCM

 

ARM968E-S

DTCM

 

 

 

DRAFT

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 Kb

 

16 Kb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s

 

 

 

 

 

DRA

 

 

 

 

m

 

 

 

 

 

 

 

 

AHB2DTL

Bridge

 

 

 

 

 

 

 

SYS_CLK

Vectored Interrupt

s

 

 

 

 

IEEE 1149.1 JTAG TEST and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEBUG INTERFACE

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller (VIC)

 

 

 

 

 

 

 

 

 

 

 

Embedded

 

 

 

 

s

 

 

External Static Memory

 

 

 

 

 

 

 

 

 

 

Controller (SMC)

 

 

 

FLASH Memory

 

 

 

 

 

 

 

 

 

 

 

512 - 768 Kb

 

 

 

 

 

 

 

 

 

 

 

FLASH Memory Controller (FMC)

 

s

 

 

 

 

Embedded

 

 

 

 

 

 

 

 

 

SRAM Memory 16 Kb

 

 

 

 

 

 

 

 

s

 

 

SRAM Controller #1

 

 

 

Modulation and Sampling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control Subsystem

 

 

 

 

 

 

 

 

 

 

MSCSS_CLK

 

 

 

 

 

 

 

 

Embedded

 

 

Timer 0, 1 (MTMR)

 

 

 

 

 

 

 

SRAM Memory 32 Kb

 

 

 

 

 

 

 

s

 

 

 

 

 

 

AHB2VPB

Bridge

 

 

 

 

 

 

 

 

 

s

 

 

 

 

SRAM Controller #0

 

 

 

 

 

 

 

 

 

 

 

 

 

PWM 0, 1, 2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC_CLK

ADC 1, 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General Subsystem

 

 

 

 

 

 

 

 

 

AHB2VPB

 

Chip Feature ID (CFID)

 

 

 

CAN Controller

 

 

 

 

s

Bridge

 

 

 

 

 

 

 

 

 

System Control Unit (SCU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0, 1

 

 

 

 

 

 

 

Event Router (ER)

 

 

IVNSS_CLK

 

AHB2VPB

Bridge

 

 

 

 

 

General Purpose IO (GPIO)

 

 

 

2 Kbyte Static RAM

s

 

 

 

 

 

 

 

GLOBAL ACCEPTANCE

 

 

 

 

 

 

Peripheral Subsystem

 

 

 

FILTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0, 1, 2, 3

 

 

 

LIN MASTER 0/1

 

 

 

 

 

 

 

Timer (TMR)

TMR_CLK

 

 

 

 

 

 

 

 

2VPBAHB

 

 

 

 

 

 

 

 

s

Bridge

0, 1, 2, 3

 

 

 

 

 

 

 

 

 

SPI_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI 0, 1, 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UART 0, 1

UART_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Watchdog Timer (WDT)

SAFE_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Clock Reset

 

 

 

 

 

 

 

 

 

 

 

Control Subsystem

 

 

 

 

 

 

 

 

 

AHB2DTL

 

Clock Generation Unit (CGU)

PCR_CLK

 

 

 

 

 

 

 

s

Bridge

 

 

 

 

 

 

 

 

Reset Generation Unit (RGU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Management Unit (PMU)

 

 

Fig 3. LPC2917/19 block diagram, overview of clock areas

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

12 of 68

Page 11 Page 13
Image 12
Page 11 Page 13
Contents Introduction General descriptionAbout this document Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview …32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsSerial peripheral interface Uart clock descriptionFunctional description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configurationPower Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin descriptionLimiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact informationContents Contact information Contents SolderingPackage outline
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