NXP Semiconductors LPC2917, LPC2919 user manual 6 PWM, ADC clock description

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

T DRAFT

T

 

DRA

DRA

 

DR

 

F

F

 

 

8.7.5.4 ADC clock description

DRAFT DRAFT DRAF

 

 

 

 

The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_VPB and

 

 

 

DRAFT DRAFT

CLK_ADCx (x = 1 or 2), see Section 7.2.2. Note that each ADC has its own CLK ADCx

 

 

and CLK_MSCSS_ADCx_VPB branch clocks for power management. If an ADC is

DRAFT

D

unused both its CLK_MSCSS_ADCx_VPB and CLK_ADCx can be switched off.

 

 

 

 

The frequency of all the CLK_MSCSS_ADCx_VPB clocks is identical to

 

 

DRA

CLK_MSCSS_VPB since they are derived from the same base clock

 

 

 

 

 

 

BASE_MSCSS_CLK. Likewise the frequency of all the CLK_ADCx clocks is identical since they are derived from the same base clock BASE_ADC_CLK.

The register interface towards the system bus is clocked by CLK_MSCSS_ADCx_VPB.

Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also

Figure 9.

8.7.6PWM

8.7.6.1Overview

The MSCSS in the LPC2917/19 includes four PWM modules with the following features.

•Six pulse-width modulated output signals

•Double edge features (rising and falling edges programmed individually)

•Optional interrupt generation on match (each edge)

•Different operation modes: continuous or run-once

•16-bit PWM counter and 16-bit prescale counter allow a large range of PWM periods

•A protective mode (TRAP) holding the output in a software-controllable state and with optional interrupt generation on a trap event

•Three capture registers and capture trigger pins with optional interrupt generation on a capture event

•Interrupt generation on match event, capture event, PWM counter overflow or trap event

•A burst mode mixing the external carrier signal with internally generated PWM

•Programmable sync-delay output to trigger other PWM modules (master/slave behavior)

8.7.6.2Description

The ability to provide flexible waveforms allows PWM blocks to be used in multiple applications; e.g. automotive dimmer/lamp control and fan control. Pulse-width modulation is the preferred method for regulating power since no additional heat is generated and it is energy-efficient when compared with linear-regulating voltage control networks.

The PWM delivers the waveforms/pulses of the desired duty cycles and cycle periods. A very basic application of these pulses can be in controlling the amount of power transferred to a load. Since the duty cycle of the pulses can be controlled, the desired amount of power can be transferred for a controlled duration. Two examples of such applications are:

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents General description IntroductionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsUart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline
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