NXP Semiconductors LPC2917, LPC2919 user manual Peripheral subsystem clock description

Page 23
8.3.4.2 Description

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

•Event detection is fully asynchronous, so no clock is required

T DRAFT

T

DRA

DRA DR

F

F

DRAFT DRAFT DRAF

The event router allows the event source to be defined, its polarity and activationDRAFTtype to DRAFT

be selected and the interrupt to be masked or enabled. The event router can be used to

D

start a clock on an external event.

DRAFT

 

The vectored interrupt-controller inputs are active HIGH.

8.3.4.3Event-router pin description and mapping to register bit positions

DRA

The event router module in the LPC2917/19 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19. Table 13 shows the pins connected to the event router, and also the corresponding bit position in the event-router registers and the default polarity.

Table 13. Event-router pin connections

Symbol

Direction

Bit position

Description

Default

 

 

 

 

polarity

EXTINT0

in

0

external interrupt input 0

1

 

 

 

 

 

EXTINT1

in

1

external interrupt input 1

1

 

 

 

 

 

EXTINT2

in

2

external interrupt input 2

1

 

 

 

 

 

EXTINT3

in

3

external interrupt input 3

1

 

 

 

 

 

EXTINT4

in

4

external interrupt input 4

1

 

 

 

 

 

EXTINT5

in

5

external interrupt input 5

1

 

 

 

 

 

EXTINT6

in

6

external interrupt input 6

1

 

 

 

 

 

EXTINT7

in

7

external interrupt input 7

1

 

 

 

 

 

CAN0 RXD

in

8

CAN0 receive data input wake-up

0

 

 

 

 

 

CAN1 RXD

in

9

CAN1 receive data input wake-up

0

 

 

 

 

 

-

-

13 - 10

reserved

-

 

 

 

 

 

LIN0 RXD

in

14

LIN0 receive data input wake-up

0

 

 

 

 

 

LIN1 RXD

in

15

LIN1 receive data input wake-up

0

 

 

 

 

 

-

-

21 - 16

reserved

-

 

 

 

 

 

-

na

22

CAN interrupt (internal)

1

 

 

 

 

 

-

na

23

VIC FIQ (internal)

1

 

 

 

 

 

-

na

24

VIC IRQ (internal)

1

 

 

 

 

 

-

-

26 - 25

reserved

-

 

 

 

 

 

8.4Peripheral subsystem

8.4.1Peripheral subsystem clock description

The peripheral subsystem is clocked by a number of different clocks:

•CLK_SYS_PESS

•CLK_UART0/1

•CLK_SPI0/1/2

•CLK_TMR0/1/2/3

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

23 of 68

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Contents Intended audience IntroductionGeneral description About this documentOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0LQFP144 pin SymbolPin Description Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsFunctional description Serial peripheral interfaceUart clock description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering
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