NXP Semiconductors LPC2917, LPC2919 user manual Features, On-chip static RAM, General

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NXP Semiconductors

DRAFT

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AFT

RAFT

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DR

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DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

DRA

 

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DR

 

 

F

 

 

F

 

2.4 On-chip static RAM

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DRAFT

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In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories:

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one of 32 kB and one of 16 kB. Both may be used for code and/or data storage. Each

 

 

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internal SRAM has its own controller, so both memories can be accessed simultaneously

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from different AHB system bus layers.

 

 

DRAFT

 

 

 

 

 

 

3. Features

 

 

 

 

 

DRA

 

 

 

 

 

 

 

3.1

General

 

 

 

 

 

 

 

„ ARM968E-S processor at 80 MHz maximum

 

 

 

 

 

 

 

„ Multi-layer AHB system bus at 80 MHz with three separate layers

 

 

 

 

 

 

„ On-chip memory:

 

 

 

 

 

 

 

‹ Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM), 16 kB Data TCM

 

 

(DTCM)

 

 

 

 

 

 

 

‹ Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

‹ Up to 768 kB flash-program memory

 

 

 

 

 

 

 

„ Two-channel CAN controller supporting Full-CAN and extensive message filtering

 

 

 

 

 

„ Two LIN master controllers with full hardware support for LIN communication

 

 

 

 

 

 

„ Two 550 UARTs with 16-byte Tx and Rx FIFO depths

 

 

 

 

 

 

 

„ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx

 

 

FIFO and Rx FIFO

 

 

 

 

 

 

 

„ Four 32-bit timers each containing four capture-and-compare registers linked to I/Os

 

 

 

 

„ 32-bit watchdog with timer change protection, running on safe clock.

 

 

 

 

 

 

„ Up to 108 general-purpose I/O pins with programmable pull-up, pull-down or bus

 

 

 

 

 

keeper

 

 

 

 

 

 

 

„ Vectored Interrupt Controller (VIC) with 16 priority levels

 

 

 

 

 

 

 

„ Two 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion

 

 

 

 

times as low as 2.44 μs per channel. Each channel provides a compare function to

 

 

 

 

minimize interrupts

 

 

 

 

 

 

 

„ Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake- up

 

 

 

 

 

features

 

 

 

 

 

 

 

„ External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data

 

 

 

 

bus; up to 24-bit address bus

 

 

 

 

 

 

 

„ Processor wake-up from power-down via external interrupt pins; CAN or LIN activity

 

 

 

 

„ Flexible Reset Generator Unit (RGU) able to control resets of individual modules

 

 

 

 

 

„ Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual

 

 

 

 

modules

 

 

 

 

 

 

 

‹ On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to

 

 

 

 

provide a Safe_Clock source for system monitoring

 

 

 

 

 

 

 

‹ On-chip crystal oscillator with operating range from 10 MHz to 50 MHz - max. PLL

 

 

input 15 MHz

 

 

 

 

 

 

 

‹ On-chip PLL allows CPU operation up to a maximum CPU rate of 80 MHz

 

 

 

 

 

 

‹ Generation of up to 10 base clocks

 

 

 

 

 

 

 

‹ Seven fractional dividers

 

 

 

 

 

 

LPC2917_19_1

 

© NXP B.V. 2007. All rights reserved.

 

 

Preliminary data sheet

Rev. 1.01 — 15 November 2007

3 of 68

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Contents Intended audience IntroductionGeneral description About this documentNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Symbol Pin DescriptionLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionTimer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsSerial peripheral interface Uart clock descriptionFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGUPower Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controllerLimiting values VIC pin descriptionVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal informationContents Contact information Contents SolderingPackage outline
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