NXP Semiconductors LPC2919 user manual Block diagram, LPC2917/19 block diagram

Page 5

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

5. Block diagram

T DRAFT

T

DRA

DRA DR

F

F

DRAFT DRAFT DRAF

 

 

 

 

 

 

 

 

DRAFT DRAFT

 

 

 

 

 

 

 

 

DRAFT

D

LPC2917/19

 

ITCM

 

ARM968E-S

DTCM

 

 

 

 

 

DRA

 

16 Kb

 

16 Kb

 

 

 

 

 

 

 

 

 

 

 

 

s

m

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vectored Interrupt

AHB2DTL

Bridge

s

 

 

 

 

IEEE 1149.1 JTAG TEST and

 

 

 

 

 

DEBUG INTERFACE

 

 

 

 

 

 

 

Controller (VIC)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Embedded

 

 

 

 

s

 

 

External Static Memory

 

 

 

 

 

 

 

 

Controller (SMC)

 

FLASH Memory

 

 

 

 

 

 

 

 

 

512/768 Kb

 

 

 

 

 

 

 

 

 

FLASH Memory Controller (FMC)

 

s

 

 

 

 

Embedded

 

 

 

 

 

 

 

SRAM Memory 16 Kb

 

 

 

 

 

 

s

 

 

SRAM Controller #1

 

Modulation and Sampling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control Subsystem

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Embedded

 

Timer 0, 1 (MTMR)

 

 

 

 

s

 

 

SRAM Memory 32 Kb

 

 

AHB2VPB

 

 

 

 

 

 

 

 

Bridge

s

 

 

 

 

SRAM Controller #0

 

PWM 0, 1, 2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General Subsystem

 

ADC 1, 2

 

 

 

 

 

B

 

Chip Feature ID (CFID)

 

 

 

 

 

 

s

 

 

 

 

 

 

 

 

HB2VP

Bridge

System Control Unit (SCU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

Event Router (ER)

 

CAN Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0, 1

 

 

 

 

 

 

 

 

 

GLOBAL ACCEPTANCE

AHB2VPB

Bridge

s

 

 

 

Peripheral Subsystem

 

FILTER

 

 

 

 

 

General Purpose IO (GPIO)

 

2 Kbyte Static RAM

 

 

 

 

 

 

 

 

 

 

 

0, 1, 2, 3

 

 

 

 

 

 

 

 

 

 

LIN MASTER 0/1

 

 

 

 

 

AHB2VPB

 

Timer (TMR)

 

 

 

 

 

 

s

B ridge

0, 1, 2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI 0, 1, 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UART 0, 1

 

 

 

 

 

 

 

 

 

Watchdog Timer (WDT)

 

 

 

 

 

 

 

 

 

Power Clock Reset

 

 

 

 

 

 

 

 

 

Control Subsystem

 

 

 

 

 

 

 

HB2DTL

 

Clock Generation Unit (CGU)

 

 

 

 

 

 

s

Bridge

Reset Generation Unit (RGU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

Power Management Unit (PMU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multi-layer AHB

 

m = master port

 

 

 

 

 

 

system bus

 

s = slave port

 

 

Fig 1. LPC2917/19 block diagram

 

 

 

 

 

 

 

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

5 of 68

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Contents General description IntroductionAbout this document Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsFunctional description Serial peripheral interfaceUart clock description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering
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