NXP Semiconductors LPC2919, LPC2917 Flash memory controller pin description, Flash layout

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Both buffer lines are invalidated after:

•Initialization

•Configuration-register access

•Data-latch reading

•Index-sector reading

The modes of operation are listed in Table 8.

T DRAFT

T

 

DRA

DRA DR

F

F

 

DRAFT DRAFT DRAF

DRAFT DRAFT

 

DRAFT

D

 

 

 

DRA

Table 8.

Flash read modes

Synchronous timing

 

 

 

No buffer line

for single (non-linear) reads; one flash-word read per word read

 

 

Single buffer line

default mode of operation; most recently read flash word is kept until

 

 

another flash word is required

 

 

Asynchronous timing

 

 

 

No buffer line

one flash-word read per word read

 

 

Single buffer line

most recently read flash word is kept until another flash word is

 

 

required

 

 

Dual buffer line, single

on a buffer miss a flash read is done, followed by at most one

speculative

 

speculative read; optimized for execution of code with small loops

 

 

(less than eight words) from flash

 

 

Dual buffer line, always

most recently used flash word is copied into second buffer line; next

speculative

 

flash-word read is started; highest performance for linear reads

 

 

 

8.1.3Flash memory controller pin description

The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see Section 7.1.3.

8.1.4Flash memory controller clock description

The flash memory controller is clocked by CLK_SYS_FMC, see Section 7.2.2.

8.1.5Flash layout

The ARM processor can program the flash for ISP (In-System Programming) and IAP (In- Application Programming). Note that the flash always has to be programmed by ‘flash words’ of 128 bits (four 32-bit AHB bus words, hence 16 bytes).

The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’ sectors of 64 kB each. The number of large sectors depends on the device type. A sector must be erased before data can be written to it. The flash memory also has sector-wise protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small sector contains 16 pages; a large sector contains 128 pages.

Table 9 gives an overview of the flash-sector base addresses.

 

Table 9.

Flash sector overview

 

 

Sector number

Sector size (kB)

Sector base address

0

 

8

0000 0000h

 

 

 

 

 

1

 

8

0000 2000h

 

 

 

 

 

2

 

8

0000 4000h

LPC2917_19_1

 

 

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

16 of 68

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Contents Introduction General descriptionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview …External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsUart clock description Serial peripheral interfaceFunctional description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterAnalog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configurationRGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin descriptionVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Soldering Contact information ContentsPackage outline
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