NXP Semiconductors LPC2919, LPC2917 user manual Vectored interrupt controller, PMU pin description

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

			T	DRAFT				T
			DRA			DRA				DR
			F				F
Legend:			DRAFT DRAFT						DRAF
Table 27. Branch clock overview …continued
"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored					DRAFT		DRAFT
"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored					DRAFT		DRAFT

“+” Indicates that the related register bit is readable and writable										D
										D
Branch Clock Name	Base Clock	Implemented Switch On/Off				DRAFT
Branch Clock Name	Base Clock	Implemented Switch On/Off
		Mechanism							DRA
		WAKEUP	AUTO		RUN				DRA
		WAKEUP	AUTO		RUN
CLK_SPI0	BASE_SPI_CLK	+	+		+

CLK_SPI1	BASE_SPI_CLK	+	+		+

CLK_SPI2	BASE_SPI_CLK	+	+		+

CLK_TMR0	BASE_TMR_CLK	+	+		+

CLK_TMR1	BASE_TMR_CLK	+	+		+

CLK_TMR2	BASE_TMR_CLK	+	+		+

CLK_TMR3	BASE_TMR_CLK	+	+		+

CLK_ADC1	BASE_ADC_CLK	+	+		+

CLK_ADC2	BASE_ADC_CLK	+	+		+

CLK_TESTSHELL_IP	BASE_CLK_TESTSHELL	0	0		1

8.8.6.3PMU pin description

The PMU has no external pins.

8.9Vectored interrupt controller

8.9.1Overview

The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request.

The key features are:

•Level-active interrupt request with programmable polarity

•56 interrupt-request inputs

•Software-interrupt request capability associated with each request input

•Observability of interrupt-request state before masking

•Software-programmable priority assignments to interrupt requests up to 15 levels

•Software-programmable routing of interrupt requests towards the ARM-processor inputs IRQ and FIQ

•Fast identification of interrupt requests through vector

•Support for nesting of interrupt service routines

8.9.2Description

The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows:

•Target 0 is ARM processor FIQ (fast interrupt service)

•Target 1 is ARM processor IRQ (standard interrupt service)

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

50 of 68

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Contents About this document IntroductionGeneral description Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview …External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsPin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsFunctional description Serial peripheral interfaceUart clock description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configurationRGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin descriptionVIC clock description Limiting valuesVIC pin description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Package outline Contact information ContentsSoldering