NXP Semiconductors LPC2917, LPC2919 Base clock and branch clock relationship, This branch clock

Page 13

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

DRA

 

DRA

 

DR

 

 

 

F

 

 

F

 

7.2.2 Base clock and branch clock relationship

T DRAFT

 

 

T

 

DRAFT DRAFT DRAF

 

 

 

 

The next table contains an overview of all the base blocks in the LPC2917/19 and their

 

 

 

 

 

derived branch clocks. A short description is given of the hardware parts that are clocked

 

 

 

 

 

 

DRAFT

DRAFT

 

with the individual branch clocks. In relevant cases more detailed information can be

 

 

 

 

D

 

found in the specific subsystem description. Some branch clocks have special protection

 

 

 

 

 

 

 

 

 

DRAFT

 

 

since they clock vital system parts of the device and should (for example) not be switched

DRA

 

off. See Section 8.8.6 for more details of how to control the individual branch clocks.

 

 

 

 

Table 7. Base clock and branch clock overview

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base clock

Branch clock name

Parts of the device clocked by

Remark

 

 

 

 

 

 

 

this branch clock

 

 

 

 

 

 

 

BASE_SAFE_CLK

CLK_SAFE

Watchdog Timer

[1]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BASE_SYS_CLK

CLK_SYS_CPU

ARM968E-S and TCMs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_SYS

AHB Bus infrastructure

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_PCRSS

AHB side of bridge in PCRSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_FMC

Flash-Memory Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_RAM0

Embedded SRAM Controller 0

 

 

 

 

 

 

 

 

 

(32 KByte)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_RAM1

Embedded SRAM Controller 1

 

 

 

 

 

 

 

 

 

(16 KByte)

 

 

 

 

 

 

 

 

CLK_SYS_SMC

External Static-Memory

 

 

 

 

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_GESS

General Subsystem

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_VIC

Vectored Interrupt Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_PESS

Peripheral Subsystem

[2] [4]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_GPIO0

GPIO bank 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_GPIO1

GPIO bank 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_GPIO2

GPIO bank 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_GPIO3

GPIO bank 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_SYS_IVNSS_A

AHB side of bridge of IVNSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BASE_PCR_CLK

CLK_PCR_SLOW

PCRSS, CGU, RGU and PMU

[1], [3]

 

 

 

 

 

 

 

logic clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BASE_IVNSS_CLK

CLK_IVNSS_VPB

VPB side of the IVNSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IVNSS_CANCA

CAN controller Acceptance Filter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IVNSS_CANC0

CAN channel 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IVNSS_CANC1

CAN channel 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IVNSS_LIN0

LIN channel 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IVNSS_LIN1

LIN channel 1

 

 

 

 

 

 

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

13 of 68

Page 12 Page 14
Image 13
Page 12 Page 14
Contents General description IntroductionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsUart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline
Top Page Image Contents