NXP Semiconductors LPC2917 Clocking strategy, Ieee 1149.1 interface pins Jtag boundary-scan test

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

 

DRA

DRAFT

DRA

 

DR

 

 

 

 

F

 

 

F

 

7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)

T

 

 

 

T

 

DRAFT DRAFT DRAF

 

 

 

 

 

The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also

 

 

DRAFT

 

referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test

 

 

 

 

 

DRAFT

 

pins can be used to connect a debugger probe for the embedded ARM processor. Pin

DRAFT

D

 

JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the

 

 

 

boundary- scan test pins.

 

 

 

 

 

 

 

 

 

 

 

DRA

 

Table 5.

IEEE 1149.1 boundary-scan test and debug interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Description

 

 

 

 

 

 

 

 

 

JTAGSEL

 

TAP controller select input. LOW level selects ARM debug mode and HIGH level

 

 

 

 

 

 

 

selects boundary scan and flash programming; pulled up internally

 

 

 

 

 

 

 

 

TRSTN

 

test reset input; pulled up internally (active LOW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

test-mode select input; pulled up internally

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

test data input, pulled up internally

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

test data output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

test clock input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.1.4Power supply pins description

Table 6 shows the power supply pins.

Table 6.

Power supplies

Symbol

 

Description

VDD(CORE)

 

digital core supply 1.8 V

VSS(CORE)

 

digital core ground (digital core, ADC 1)

VDD(IO)

 

I/O pins supply 3.3 V

VSS(IO)

 

I/O pins ground

VDD(OSC)

 

oscillator and PLL supply

VSS(OSC)

 

oscillator ground

VDD(A3V3)

 

ADC 3.3 V supply

VSS(PLL)

 

PLL ground

7.2Clocking strategy

7.2.1Clock architecture

The LPC2917/19 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in frequency and phase and can have different clock sources within the CGU.

The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base clock. This means most peripherals are clocked independently from the system clock. See Figure 3 for an overview of the clock areas within the device.

Within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. All branch clocks are outputs of the Power Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See Section 8.8 for more details of clock and power control within the device.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

11 of 68

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Contents Intended audience IntroductionGeneral description About this documentOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0LQFP144 pin SymbolPin Description Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsFunctional description Serial peripheral interfaceUart clock description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering
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