NXP Semiconductors LPC2917 LQFP144 pin assignment …, Symbol Pin Description Function 0 default

Page 7

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 3.	LQFP144 pin assignment …continued
Symbol	Pin	Description
		Function 0 (default)		Function 1		Function 2
		Function 0 (default)		Function 1		Function 2
P2.24	16	GPIO 2, pin 24	-			PWM3 CAP1
P2.25	17	GPIO 2, pin 25	-			PWM3 CAP2
VDD(CORE)	18	1.8 V power supply for digital core
VSS(CORE)	19	ground for digital core
P1.31	20	GPIO 1, pin 31		TIMER0 CAP1		TIMER0 MAT1
VSS(IO)	21	ground for I/O
P1.30	22	GPIO 1, pin 30		TIMER0 CAP0		TIMER0 MAT0
P3.8	23	GPIO 3, pin 8		SPI2 SCS0		PWM1 MAT2
P3.9	24	GPIO 3, pin 9		SPI2 SDO		PWM1 MAT3
P1.29	25	GPIO 1, pin 29		TIMER1 CAP0, EXT		PWM TRAP0
				START
P1.28	26	GPIO 1, pin 28		TIMER1 CAP1, ADC1		PWM TRAP1
				EXT START
P2.26	27	GPIO 2, pin 26		TIMER0 CAP2		TIMER0 MAT2
P2.27	28	GPIO 2, pin 27		TIMER0 CAP3		TIMER0 MAT3
P1.27	29	GPIO 1, pin 27		TIMER1 CAP2, ADC2		PWM TRAP2
				EXT START
P1.26	30	GPIO 1, pin 26		PWM2 MAT0		PWM TRAP3
VDD(IO)	31	3.3 V power supply for I/O
P1.25	32	GPIO 1, pin 25		PWM1 MAT0	-
P1.24	33	GPIO 1, pin 24		PWM0 MAT0	-
P1.23	34	GPIO 1, pin 23		UART0 RxD	-
P1.22	35	GPIO 1, pin 22		UART0 TxD	-
TMS	36	IEEE 1149.1 test mode select, pulled up internally.
TCK	37	IEEE 1149.1 test clock
P1.21	38	GPIO 1, pin 21		TIMER3 CAP3		TIMER1 CAP3,
						MSCSS PAUSE
P1.20	39	GPIO 1, pin 20		TIMER3 CAP2		SPI0 SCS1
P1.19	40	GPIO 1, pin 19		TIMER3 CAP1		SPI0 SCS2
P1.18	41	GPIO 1, pin 18		TIMER3 CAP0		SPI0 SDO
P1.17	42	GPIO 1, pin 17		TIMER2 CAP3		SPI0 SDI
VSS(IO)	43	ground for I/O
P1.16	44	GPIO 1, pin 16		TIMER2 CAP2		SPI0 SCK
P2.0	45	GPIO 2, pin 0		TIMER2 MAT0		PWM TRAP3
P2.1	46	GPIO 2, pin 1		TIMER2 MAT1		PWM TRAP2
P3.10	47	GPIO 3, pin 10		SPI2 SDI		PWM1 MAT4
P3.11	48	GPIO 3, pin 11		SPI2 SCK		PWM1 MAT5
P1.15	49	GPIO 1, pin 15		TIMER2 CAP1		SPI0 SCS0
P1.14	50	GPIO 1, pin 14		TIMER2 CAP0		SPI0 SCS3
P1.13	51	GPIO 1, pin 13		EXTINT3	-
P1.12	52	GPIO 1, pin 12		EXTINT2	-

T DRAFT		T
DRA		DRA		DR
F		F
DRAFT DRAFT DRAF
Function 3	DRAFT DRAFT
Function 3
EXTBUS D22		DRAFT		D
EXTBUS D23		DRAFT
EXTBUS D23
			DRA

EXTINT5

EXTINT4

-

-

PWM3 MAT5

PWM3 MAT4

EXTINT6

EXTINT7

PWM3 MAT3

PWM3 MAT2

PWM3 MAT1

PWM3 MAT0

EXTBUS CS5

EXTBUS CS4

EXTBUS D7

EXTBUS D6

EXTBUS D5

EXTBUS D4

EXTBUS D3

EXTBUS D2

EXTBUS D8

EXTBUS D9

-

-

EXTBUS D1

EXTBUS D0

EXTBUS WEN

EXTBUS OEN

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

7 of 68

Image 7

Contents Intended audience IntroductionGeneral description About this documentARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Pin Description SymbolLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsUart clock description Serial peripheral interfaceFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline