NXP Semiconductors LPC2917, LPC2919 user manual Dra

Page 49

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

				T	DRAFT				T
				DRA			DRA				DR
	Legend:			F				F
	Legend:			DRAFT DRAFT						DRAF
	Table 27. Branch clock overview
	"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored					DRAFT		DRAFT
	"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored					DRAFT		DRAFT

	“+” Indicates that the related register bit is readable and writable						DRAFT				D
	Branch Clock Name	Base Clock	Implemented Switch On/Off				DRAFT
	Branch Clock Name	Base Clock	Implemented Switch On/Off
			Mechanism							DRA
			WAKEUP	AUTO		RUN				DRA
			WAKEUP	AUTO		RUN
	CLK_SAFE	BASE_SAFE_CLK	0	0		1

	CLK_SYS_CPU	BASE_SYS_CLK	+	+		1

	CLK_SYS	BASE_SYS_CLK	+	+		1

	CLK_SYS_PCR	BASE_SYS_CLK	+	+		1

	CLK_SYS_FMC	BASE_SYS_CLK	+	+		+

	CLK_SYS_RAM0	BASE_SYS_CLK	+	+		+

	CLK_SYS_RAM1	BASE_SYS_CLK	+	+		+

	CLK_SYS_SMC	BASE_SYS_CLK	+	+		+

	CLK_SYS_GESS	BASE_SYS_CLK	+	+		+

	CLK_SYS_VIC	BASE_SYS_CLK	+	+		+

	CLK_SYS_PESS	BASE_SYS_CLK	+	+		+

	CLK_SYS_GPIO0	BASE_SYS_CLK	+	+		+

	CLK_SYS_GPIO1	BASE_SYS_CLK	+	+		+

	CLK_SYS_GPIO2	BASE_SYS_CLK	+	+		+

	CLK_SYS_GPIO3	BASE_SYS_CLK	+	+		+

	CLK_SYS_IVNSS_A	BASE_SYS_CLK	+	+		+

	CLK_SYS_MSCSS_A	BASE_SYS_CLK	+	+		+

	CLK_SYS_CHCA	BASE_SYS_CLK	+	+		+

	CLK_SYS_CHCB	BASE_SYS_CLK	+	+		+

	CLK_PCR_SLOW	BASE_PCR_CLK	+	+		1

	CLK_IVNSS_VPB	BASE_IVNSS_CLK	+	+		+

	CLK_IVNSS_CANC0	BASE_IVNSS_CLK	+	+		+

	CLK_IVNSS_CANC1	BASE_IVNSS_CLK	+	+		+

	CLK_IVNSS_LIN0	BASE_IVNSS_CLK	+	+		+

	CLK_IVNSS_LIN1	BASE_IVNSS_CLK	+	+		+

	CLK_MSCSS_VPB	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_MTMR0	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_MTMR1	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_PWM0	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_PWM1	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_PWM2	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_PWM3	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_ADC1_VPB	BASE_MSCSS_CLK	+	+		+

	CLK_MSCSS_ADC2_VPB	BASE_MSCSS_CLK	+	+		+

	CLK_UART0	BASE_UART_CLK	+	+		+

	CLK_UART1	BASE_UART_CLK	+	+		+
LPC2917_19_1				© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

49 of 68

Image 49

Contents General description IntroductionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsUart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline