NXP Semiconductors LPC2917, LPC2919 user manual PLL functional description

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT

T

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DRA

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and values of ’CLK_SEL’ that would select those clocks are masked and notDRAFTwrittenDRAFTto the

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Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid,

 

control registers. This is accomplished by adding a clock detector to every clock DRAFT DRAFT generator. The RDET register keeps track of which clocks are active and inactive, and the

appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock

DRAFT

D

 

detector can also generate interrupts at clock activation and deactivation so that the

 

system can be notified of a change in internal clock status.

DRA

 

Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After reset all clocks are assumed to be ‘non-present’, so the RDET status register will be correct only after 32 BASE_PCR_CLK cycles.

Note that this mechanism cannot protect against a currently-selected clock going from active to inactive state. Therefore an inactive clock may still be sent to the system under special circumstances, although an interrupt can still be generated to notify the system.

Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators.

In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch will occur as quickly as possible, although there will always be a period when the clock is held low due to synchronization requirements.

If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the interface.

8.8.4.3PLL functional description

A block diagram of the PLL is shown in Figure 14. The input clock is fed directly to the analog section. This block compares the phase and frequency of the inputs and generates the main clock2. These clocks are either divided by 2*P by the programmable post divider to create the output clock, or sent directly to the output. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock.

2.Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 31, Dynamic characteristics.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents General description IntroductionAbout this document Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsSerial peripheral interface Uart clock descriptionFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGUPower Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controllerLimiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal informationContents Contact information Contents SolderingPackage outline
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