NXP Semiconductors LPC2919, LPC2917 Ordering information, Ordering options, Part options

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

	T	DRAFT			T
	DRA			DRA		DR
	F				F	DRAF
Highly configurable system Power Management Unit (PMU),	DRAFT		DRAFT			DRAF
Highly configurable system Power Management Unit (PMU),
clock control of individual modules					DRAFT
		DRAFT			DRAFT
allows minimization of system operating power consumption in any configuration
Standard ARM test and debug interface with real-time in-circuit emulator				DRAFT		D
Boundary-scan test supported				DRAFT
Boundary-scan test supported
Dual power supply:						DRA
CPU operating voltage: 1.8 V ± 5%						DRA
CPU operating voltage: 1.8 V ± 5%

I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V 144-pin LQFP package

−40 °C to 85 °C ambient operating temperature range

4. Ordering information

Table 1. Ordering information

Type number

Package

Name	Description

Version

LPC2917FBD144	LQFP144	plastic low profile quad flat package; 144 leads; body 20 ⋅ 20 ⋅ 1.4 mm, pin	SOT486-1
		pitch 0.5 mm

LPC2919FBD144	LQFP144	plastic low profile quad flat package; 144 leads; body 20 ⋅ 20 ⋅ 1.4 mm, pin	SOT486-1
		pitch 0.5 mm

4.1 Ordering options

Table 2. Part options

Type number	Flash memory	RAM (kB)	SMC	LIN 2.0	Package
	(kB)
LPC2917FBD144	512	80 (incl TCMs)	32-bit	2	LQFP144

LPC2919FBD144	768	80 (incl TCMs)	32-bit	2	LQFP144

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents Introduction General descriptionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview …External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsUart clock description Serial peripheral interfaceFunctional description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterAnalog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configurationRGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin descriptionVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Soldering Contact information ContentsPackage outline