NXP Semiconductors LPC2919 Modes of operation, SPI pin description, SPI clock description

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

T DRAFT

T

 

 

DRA

DRA

 

DR

 

F

F

 

Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an

 

DRAF

active-HIGH frame synchronization output for Texas Instruments synchronousDRAFTserialDRAFT

 

 

frame format or an active-LOW chip select for SPI.

DRAFT DRAFT

 

 

 

 

Each data frame is between four and 16 bits long, depending on the size of words

DRAFT

D

programmed, and is transmitted starting with the MSB.

 

 

 

 

 

 

There are two basic frame types that can be selected:

•Texas Instruments synchronous serial

•Motorola Serial Peripheral Interface

8.4.5.3Modes of operation

The SPI module can operate in:

•Master mode:

–Normal transmission mode

–Sequential slave mode

•Slave mode

8.4.5.4SPI pin description

The three SPI modules in the LPC2917/19 have the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3. Table 16 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3).

Table 16. SPI pins

DRA

Symbol

Direction

Description

SPIx SCSy

in/out

SPIx chip select[1][2]

SPIx SCK

in/out

SPIx clock[1]

SPIx SDI

in

SPIx data input

 

 

 

SPIx SDO

out

SPIx data output

 

 

 

[1]Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode.

[2]In slave mode there is only one chip-select input pin, SPIx SCS0. The other chip selects have no function in slave mode.

8.4.5.5SPI clock description

The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx (x = 0-2), see Section 7.2.2. Note that each SPI has its own CLK_SPIx branch clock for power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.

The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on the interface.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

28 of 68

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Contents Introduction General descriptionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview …External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsUart clock description Serial peripheral interfaceFunctional description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterAnalog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configurationRGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin descriptionVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Soldering Contact information ContentsPackage outline
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