NXP Semiconductors LPC2919, LPC2917 Power Management Unit PMU, RGU pin description, RGU pins

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

T

DRAFT

 

 

T

 

 

 

 

DRA

 

DRA

 

DR

 

 

 

F

 

 

F

 

 

8.8.5.3 RGU pin description

DRAFT DRAFT DRAF

 

 

 

 

 

 

 

 

The RGU module in the LPC2917/19 has the following pins. Table 26 shows the RGU

DRAFT

 

pins.

 

 

DRAFT

 

 

 

 

 

 

 

 

 

 

Table 26.

RGU pins

 

 

DRAFT

D

 

 

 

 

 

Symbol

Directio

Description

 

 

 

 

n

 

 

 

 

 

DRA

 

RSTN

IN

external reset input, Active LOW; pulled up internally

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8.8.6Power Management Unit (PMU)

8.8.6.1Overview

This module enables software to actively control the system’s power consumption by disabling clocks not required in a particular operating mode.

Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2917/19. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming.

The key features are:

•Individual clock control for all LPC2917/19 sub-modules

•Activates sleeping clocks when a wake-up event is detected

•Clocks can be individually disabled by software

•Supports AHB master-disable protocol when AUTO mode is set

•Disables wake-up of enabled clocks when power-down mode is set

•Activates wake-up of enabled clocks when a wake-up event is received

•Status register is available to indicate if an input base clock can be safely switched off (i.e. all branch clocks are disabled)

8.8.6.2Description

The PMU controls all internal clocks of the device for power-mode management. With some exceptions, each branch clock can be switched on or off individually under control of software register bits located in its individual configuration register. Some branch clocks controlling vital parts of the device operate in a fixed mode. Table 27 shows which mode- control bits are supported by each branch clock.

By programming the configuration register the user can control which clocks are switched on or off, and which clocks are switched off when entering power-down mode.

Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU into power-down should be controlled by disabling the branch clock for the CPU.

Remark: For any disabled branch clocks to be re-activated their corresponding base clocks must be running (controlled by the CGU).

Table 27 shows the relation between branch and base clocks, see also Section 7.2.1. Every branch clock is related to one particular base clock: it is not possible to switch the source of a branch clock in the PMU.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

48 of 68

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Contents Introduction General descriptionAbout this document Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview …32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsSerial peripheral interface Uart clock descriptionFunctional description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configurationPower Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin descriptionLimiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact informationContents Contact information Contents SolderingPackage outline
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