NXP Semiconductors LPC2917, LPC2919 user manual Draft, Analog-to-digital converter

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NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

T DRAFT

 

T

 

 

DRA

 

DRA

DR

 

 

F

DRAFT

F

•

 

DRAFT

 

DRAF

CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge

 

 

 

 

•

CLK_MSCSS_VPB clocks the subsystem VPB bus

DRAFT

DRAFT

•

CLK_MSCSS_MTMR0/1 clocks the timers

 

 

 

 

 

•

CLK_MSCSS_PWM0..3 clocks the PWMs.

 

 

 

 

D

 

 

 

 

DRAFT

Each ADC has two clock areas; a VPB part clocked by CLK_MSCSS_ADCx_VPB (x = 1

 

DRA

or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see

 

 

Section 7.2.2.

All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding clocks can be switched off.

8.7.5Analog-to-digital converter

8.7.5.1Overview

The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation analog-to-digital converters.

The key features of the ADC interface module are:

•ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to 3.3 V

•External reference-level inputs

•400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit resolution

•Programmable resolution from 2-bit to 10-bit

•Single analog-to-digital conversion scan mode and continuous analog-to-digital conversion scan mode

•Optional conversion on transition on external start input, timer capture/match signal, PWM_sync or ‘previous’ ADC

•Converted digital values are stored in a register for each channel

•Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’ compare-value indication for each channel

•Power-down mode

8.7.5.2Description

The ADC block diagram, Figure 9, shows the basic architecture of each ADC. The ADC functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain.

A mechanism is provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

35 of 68

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Contents Intended audience IntroductionGeneral description About this documentOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0LQFP144 pin SymbolPin Description Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsFunctional description Serial peripheral interfaceUart clock description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering
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