NXP Semiconductors LPC2917 General-purpose I/O, Overview, Gpio pin description, Gpio pins

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

			DRA	DRA			DR
			F		F
	8.4.6	General-purpose I/O	T DRAFT		T
	8.4.6	General-purpose I/O	DRAFT DRAFT DRAF
	8.4.6.1	Overview	DRAFT DRAFT DRAF
	8.4.6.1	Overview			DRAFT
		The LPC2917/19 contains four general-purpose I/O ports located at different peripheralDRAFT			DRAFT
							D
		base addresses. In the 144-pin package all four ports are available. All I/O pins are					D

		bi-directional, and the direction can be programmed individually. The I/O pad behavior DRAFT
		depends on the configuration programmed in the port function-select registers.				DRA
						DRA

The key features are:

• General-purpose parallel inputs and outputs

• Direction control of individual bits

• Synchronized input sampling for stable input-data values

• All I/O defaults to input at reset to avoid any possible bus conflicts

8.4.6.2 Description

The general-purpose I/O provides individual control over each bi-directional port pin. There are two registers to control I/O direction and output level. The inputs are synchronized to achieve stable read-levels.

To generate an open-drain output, set the bit in the output register to the desired value. Use the direction register to control the signal. When set to output, the output driver actively drives the value on the output: when set to input the signal floats and can be pulled up internally or externally.

8.4.6.3 GPIO pin description

The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2917/19. Table 17 shows the GPIO pins.

Table 17. GPIO pins

Symbol	Direction	Description
GPIO0 pin[31:0]	in/out	GPIO port x pins 31 to 0

GPIO1 pin[31:0]	in/out	GPIO port x pins 31 to 0

GPIO2 pin[27:0]	in/out	GPIO port x pins 27 to 0

GPIO3 pin[15:0]	in/out	GPIO port x pins 15 to 0

8.4.6.4GPIO clock description

The GPIO modules are clocked by several clocks, all of which are derived from

BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0-3), see Section 7.2.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

29 of 68

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Contents General description IntroductionAbout this document Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsFunctional description Serial peripheral interfaceUart clock description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering