NXP Semiconductors LPC2917 Timers in the Mscss, Master and slave mode, PWM pin description

Page 39

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

DRA

DRA

 

DR

 

F

F

 

8.7.6.4 Master and slave mode

T DRAFT

T

 

DRAFT DRAFT DRAF

 

A PWM module can provide synchronization signals to other modules (also called Master

 

 

mode). The signal sync_out is a pulse of one clock cycle generated when the internal

 

 

 

DRAFT DRAFT

PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync

out,

 

D

generated if a transfer from system registers to PWM shadow registers occurred when the

 

 

 

PWM counter restarted. A delay may be inserted between the counter start and

DRAFT

 

 

DRA

generation of trans_enable_out and sync_out.

 

 

A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode).

8.7.6.5 PWM pin description

Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2917/19. Table 21 shows the PWM0 to PWM3 pins.

Table 21. PWM pins

Symbol

Direction

Description

PWMn CAP[0]

in

PWM n capture input 0

 

 

 

PWMn CAP[1]

in

PWM n capture input 1

 

 

 

PWMn CAP[2]

in

PWM n capture input 2

 

 

 

PWMn MAT[0]

out

PWM n match output 0

 

 

 

PWMn MAT[1]

out

PWM n match output 1

 

 

 

PWMn MAT[2]

out

PWM n match output 2

 

 

 

PWMn MAT[3]

out

PWM n match output 3

 

 

 

PWMn MAT[4]

out

PWM n match output 4

 

 

 

PWMn MAT[5]

out

PWM n match output 5

 

 

 

PWMn TRAP

in

PWM n trap input

 

 

 

8.7.6.6PWM clock description

The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0-3), see Section 7.2.2. Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB since they are derived from the same base clock BASE_MSCSS_CLK.

Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer counter registers of the PWM modules run at the same clock as the VPB system interface CLK_MSCSS_VPB. This clock is independent of the AHB system clock.

If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.

8.7.7Timers in the MSCSS

8.7.7.1Overview

The two timers in the MSCSS are functionally identical to the timers in the peripheral subsystem, see Section 8.4.3. The features of the timers in the MSCSS are the same as the timers in the peripheral subsystem, but the capture inputs and match outputs are not available on the device pins. These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS, see Section 8.7.2.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

39 of 68

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Contents Intended audience IntroductionGeneral description About this documentNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Symbol Pin DescriptionLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionTimer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsSerial peripheral interface Uart clock descriptionFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGUPower Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controllerLimiting values VIC pin descriptionVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal informationContents Contact information Contents SolderingPackage outline
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