NXP Semiconductors LPC2919, LPC2917 user manual Synchronization and trigger features of the Mscss

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T	DRAFT			T
DRA		DRA				DR
F				F
or following a PWM). The capture inputs of both timers can also be used toDRAFTcaptureDRAFTthe					DRAF
control. Several other trigger possibilities are provided for the ADCs (external, cascaded
start pulse of the ADCs.	DRAFT DRAFT
start pulse of the ADCs.
The PWMs can be used to generate waveforms in which the frequency, duty cycle and						D
			DRAFT
rising and falling edges can be controlled very precisely. Capture inputs are provided to
measure event phases compared to the main counter. Depending on the applications,					DRA
these inputs can be connected to digital sensor motor outputs or digital external signals.					DRA

Interrupt signals are generated on several events to closely interact with the CPU.

The ADCs can be used for any application needing accurate digitized data from analog sources. To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out).

Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see

Section 8.8.4 .

ADC2 IN[7:0]
ADC2_EXT_START
ADC1 IN[7:0]
ADC1_EXT_START
ADC clock
		MSCSS
		TIMER 0
		ADC	ADC
		CONTROL	1
				ADC
AHB	VPB sub system bus	SYNCS	3.3 V	2
AHB	VPB sub system bus	SYNCS
system bus	(to all sub blocks)			3.3 V
AHB2VPB				3.3 V
AHB2VPB
BRIDGE				PWM0 MAT[5:0]
		MSCSS	PWM	PWM0 MAT[5:0]
		MSCSS	PWM
		TIMER 1	0	PWM1 MAT[5:0]
			PWM
		PWM	1	PWM2 MAT[5:0]
		CONTROL	PWM
			2	PWM3 MAT[5:0]
		CARRIERS		PWM
		CARRIERS		3
				3
PWM0 TRAP
PWM0 CAP[2:0]
PWM1 TRAP
PWM1 CAP[2:0]
PWM2 TRAP
PWM2 CAP[2:0]
PWM3 TRAP
PWM3 CAP[2:0]				002aad348
Fig 7. Modulation and sampling control subsystem block diagram

8.7.2.1Synchronization and trigger features of the MSCSS

The MSCSS contains two internal timers to generate synchronization and carrier pulses for the ADCs and PWMs. Figure 8 shows how the timers are connected to the ADC and PWM modules.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

32 of 68

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Contents Introduction General descriptionAbout this document Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview …External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsPin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsFunctional description Serial peripheral interfaceUart clock description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configurationRGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin descriptionVIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Package outline Contact information ContentsSoldering