NXP Semiconductors LPC2917, LPC2919 user manual Symbol, Pin Description, LQFP144 pin

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 3.

Symbol

P0.0

VSS(IO)

P0.1

P0.2

P0.3

P3.0

P3.1

P2.12

P2.13

P0.4

P0.5

VDD(IO)

P0.6

P0.7

VDD(A3V3)

JTAGSEL

NC

VREFP

VREFN

P0.8

P0.9

P0.10

P0.11

P2.14

P2.15

P3.2

VSS(IO)

P3.3

P0.12

P0.13

P0.14

P0.15

P0.16

P0.17

VDD(CORE)

VSS(CORE)

P2.16

P2.17

VDD(IO)

				T DRAFT				T
				DRA			DRA			DR
				F			F
Pin	Description			DRAFT		DRAFT DRAF
LQFP144 pin	assignment …continued
								DRAFT
	Function 0 (default)	Function 1	Function 2	Function 3	DRAFT			DRAFT
	Function 0 (default)	Function 1	Function 2	Function 3
93	GPIO 0, pin 0	-	CAN0 TxD	EXTBUS D24			DRAFT			D
94	ground for I/O						DRAFT
94	ground for I/O
95	GPIO 0, pin 1	-	CAN0 RxD	EXTBUS D25					DRA
96	GPIO 0, pin 2	-	PWM0 MAT0	EXTBUS D26					DRA
96	GPIO 0, pin 2	-	PWM0 MAT0	EXTBUS D26
97	GPIO 0, pin 3	-	PWM0 MAT1	EXTBUS D27
98	GPIO 3, pin 0	-	PWM2 MAT0	EXTBUS CS6
99	GPIO 3, pin 1	-	PWM2 MAT1	EXTBUS CS7
100	GPIO 2, pin 12	-	PWM0 MAT4	SPI0 SDI
101	GPIO 2, pin 13	-	PWM0 MAT5	SPI0 SDO
102	GPIO 0, pin 4	-	PWM0 MAT2	EXTBUS D28
103	GPIO 0, pin 5	-	PWM0 MAT3	EXTBUS D29
104	3.3 V power supply for I/O
105	GPIO 0, pin 6	-	PWM0 MAT4	EXTBUS D30
106	GPIO 0, pin 7	-	PWM0 MAT5	EXTBUS D31

1073.3 V power supply for AD Converters

108TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan and flash programming; pulled up internally

109-

110HIGH reference for AD Converters

111LOW reference for AD Converters

112	GPIO 0, pin 8	ADC1 IN0	LIN0 TxD	EXTBUS A20
113	GPIO 0, pin 9	ADC1 IN1	LIN0 RxD	EXTBUS A21
114	GPIO 0, pin 10	ADC1 IN2	PWM1 MAT0	EXTBUS A8
115	GPIO 0, pin 11	ADC1 IN3	PWM1 MAT1	EXTBUS A9
116	GPIO 2, pin 14	-	PWM0 CAP0	EXTBUS BLS0
117	GPIO 2, pin 15	-	PWM0 CAP1	EXTBUS BLS1
118	GPIO 3, pin 2	TIMER3 MAT0	PWM2 MAT2	-
119	ground for I/O
120	GPIO 3, pin 3	TIMER3 MAT1	PWM2 MAT3	-
121	GPIO 0, pin 12	ADC1 IN4	PWM1 MAT2	EXTBUS A10
122	GPIO 0, pin 13	ADC1 IN5	PWM1 MAT3	EXTBUS A11
123	GPIO 0, pin 14	ADC1 IN6	PWM1 MAT4	EXTBUS A12
124	GPIO 0, pin 15	ADC1 IN7	PWM1 MAT5	EXTBUS A13
125	GPIO 0, pin 16	ADC2 IN0	UART0 TXD	EXTBUS A22
126	GPIO 0, pin 17	ADC2 IN1	UART0 RXD	EXTBUS A23

1271.8 V power supply for digital core

128ground for digital core

129	GPIO 2, pin 16	UART1 TxD	PWM0 CAP2	EXTBUS BLS2
130	GPIO 2, pin 17	UART1 RxD	PWM1 CAP0	EXTBUS BLS3
131	3.3 V power supply for I/O

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

9 of 68

Image 9

Contents General description IntroductionAbout this document Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsSerial peripheral interface Uart clock descriptionFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGUPower Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controllerLimiting values VIC pin descriptionVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal informationContents Contact information Contents SolderingPackage outline