NXP Semiconductors LPC2919, LPC2917 user manual Mscss pin description, Mscss clock description

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

DRA

DRAFT

DRA

DR

F

F

T

T

ADC2_EXT_START

DRAFT

DRAFT DRAF

ADC1_EXT_START

DRAFT DRAFT

DRAFT

D

DRA

pause_0

pause

ADC1(2)

MSCSS(1)

st0

ADC2(2)

TIMER 0

so0

c0

m0

st1

st0

st2

so

st1

so1

c1

m1

st3

st2

so

so2

c2

m2

st3

pause_0

c3

m3

PWM0(3)

MSCSS(1)

s_i

PWM1(3)

TE_i

TIMER 1

c_i

s_o

s_i

PWM2(3)

c0

m0

TE_o

TE_i

trap

c_i

s_o

s_i

PWM3(3)

c1

m1

TE_o

TE_i

c2

m2

trap

c_i

s_o

s_i

TE_o

TE_i

trap

c_i

s_o

c3

m3

TE_o

trap

pause

MSCSS PAUSE

PWM0 TRAP

PWM1 TRAP

PWM2 TRAP

PWM3 TRAP

002aad347

(1)

Timers:

c0 to c3 = capture in 0 to capture in 3

m0 to m3 = match out 0 to match out 3

(2)

ADCs:

st0 to st3 = start 0 to start 3 inputs

s0 to s3 = sync_out 0 to sync_out 3

(3)

PWMs:

c_i = carrier in

s_i = sync_in

s_o = sync_out

TE_i = trans_enable_in

TE_o = trans_enable_out

Fig 8. Modulation and sampling-control subsystem synchronization and triggering

8.7.3MSCSS pin description

The pins of the LPC2917/19 MSCSS associated with the two ADC modules are described in Section 8.7.5.3. Pins directly connected to the four PWM modules are described in Section 8.7.6.5: pins directly connected to the MSCSS timer 1 module are described in Section 8.7.7.3.

8.7.4MSCSS clock description

The MSCSS is clocked from a number of different sources:

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

34 of 68

Image 34

Contents About this document IntroductionGeneral description Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview …External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsWatchdog timer clock description TimerPin description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsUart clock description Serial peripheral interfaceFunctional description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterAnalog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configurationRGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin descriptionVIC pin description Limiting valuesVIC clock description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Soldering Contact information ContentsPackage outline