NXP Semiconductors LPC2917, LPC2919 user manual Description, Pin description

Page 25

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

T

DRAFT

 

T

 

 

DRA

 

DRA

 

DR

 

F

 

 

F

 

 

timer has four capture inputs and/or match outputs. Connection to device pins depends on

DRAF

 

the configuration programmed into the port function-select registers. The twoDRAFTtimersDRAFT

 

 

 

located in the MSCSS have no external capture or match pins, but the memory map is

DRAFT

 

identical, see Section 8.7.7. One of these timers has an external input for a pauseDRAFT

 

function.

 

DRAFT

D

 

 

 

 

The key features are:

 

 

 

 

 

 

DRA

 

• 32-bit timer/counter with programmable 32-bit prescaler

 

 

 

 

 

 

 

 

 

 

• Up to four 32-bit capture channels per timer. These take a snapshot of the timer value

 

 

 

when an external signal connected to the TIMERx CAPn input changes state. A

 

 

 

 

 

capture event may also optionally generate an interrupt

 

 

 

 

 

 

• Four 32-bit match registers per timer that allow:

 

 

 

 

 

 

– Continuous operation with optional interrupt generation on match

 

 

 

 

 

 

– Stop timer on match with optional interrupt generation

 

 

 

 

 

 

– Reset timer on match with optional interrupt generation

 

 

 

 

 

 

• Up to four external outputs per timer corresponding to match registers, with the

 

 

 

 

 

following capabilities:

 

 

 

 

 

 

– Set LOW on match

 

 

 

 

 

 

– Set HIGH on match

 

 

 

 

 

 

– Toggle on match

 

 

 

 

 

 

– Do nothing on match

 

 

 

 

 

 

• Pause input pin (MSCSS timers only)

 

 

 

 

 

8.4.3.2

Description

 

 

 

 

 

 

The timers are designed to count cycles of the clock and optionally generate interrupts or

 

 

 

perform other actions at specified timer values, based on four match registers. They also

 

 

 

include capture inputs to trap the timer value when an input signal changes state,

 

 

 

 

 

optionally generating an interrupt. The core function of the timers consists of a 32 bit

 

 

 

 

 

‘prescale counter’ triggering the 32 bit ‘timer counter’. Both counters run on clock

 

 

 

 

 

CLK_TMRx (x runs from 0 to 3) and all time references are related to the period of this

 

 

 

 

clock. Note that each timer has its individual clock source within the Peripheral

 

 

 

 

 

SubSystem. In the Modulation and Sampling SubSystem each timer also has its own

 

 

 

 

 

individual clock source. See section Section 8.8.6 for information on generation of these

 

 

 

 

clocks.

 

 

 

 

 

8.4.3.3

Pin description

 

 

 

 

 

 

The four timers in the peripheral subsystem of the LPC2917/19 have the pins described

 

 

 

 

below. The two timers in the modulation and sampling subsystem have no external pins

 

 

 

except for the pause pin on MSCSS timer 1. See Section 8.7.7 for a description of these timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3. Table Table 14 shows the timer pins (x runs from 0 to 3).

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

25 of 68

Page 24 Page 26
Image 25
Page 24 Page 26
Contents General description IntroductionAbout this document Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering options Ordering informationOrdering information Part optionsLPC2917/19 block diagram Block diagramPinning Pinning informationPin description General descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER2 MAT3 PWM TRAP0 TIMER2 MAT2 PWM TRAP1TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset and power-up behavior Reset, debug, test and power descriptionReset strategy Reset pinPower supply pins description Ieee 1149.1 interface pins Jtag boundary-scan testClocking strategy Clock architectureLPC2917/19 LPC2917/19 block diagram, overview of clock areasBase clock and branch clock overview Base clock and branch clock relationshipBase clock Branch clock name Parts of the device clocked by This branch clockFlash memory controller Block descriptionOverview Base clockDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External memory controller pins External memory timing diagramsExternal static-memory controller pin description External static-memory controller clock descriptionWriting to external memory Reading from external memoryReading/writing external memory General subsystem Chip and feature identificationGeneral subsystem clock description System Control Unit SCUPeripheral subsystem Symbol Direction Bit position Description Default PolarityPeripheral subsystem clock description Event-router pin connectionsWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionTimer pins Timer clock descriptionUart pins UARTsUart clock description Serial peripheral interfaceFunctional description Modes of operation SPI pinsSPI pin description SPI clock descriptionGeneral-purpose I/O Gpio pins6.1 Overview Gpio pin descriptionCan gateway Can pinsLIN Global acceptance filterModulation and sampling control subsystem LIN controller pinsLIN pin description LIN0/1 TxdlModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramMaster and slave mode Timers in the MscssPWM pins PWM pin descriptionMscss timer-clock description Power, clock and reset control subsystemMscss timer 1 pin Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputVDDA5V FSR Analog-to-digital converter supplyINL LSBPower-up reset Dynamic characteristicsDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineIntroduction SolderingThrough-hole mount packages Surface mount packagesTemperature profiles for large and small components Volume mm3 350 235 220 Lead-free process from J-STD-020CWave soldering SnPb eutectic process from J-STD-020C Package thickness mmMounting Package1 Soldering method Wave Reflow2 Dipping Package related soldering informationCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline
Top Page Image Contents