NXP Semiconductors LPC2919, LPC2917 user manual Synchronizing the PWM counters, PWM block diagram

Page 38

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

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DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

 

 

 

 

 

 

 

 

 

 

T

DRAFT

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRA

 

 

 

DRA

 

DR

 

 

 

 

 

 

 

 

 

 

 

 

 

F

 

 

 

 

F

 

cycle and cycle period allows the PWM to control the amount of powerDRAFTto be

DRAFT

DRAF

• Automotive dimmer controller: The flexibility of providing waves of a desired duty

 

DRAFT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRAFT

transferred to the load. The PWM functions as a dimmer controller in this application

 

 

• Motor controller: The PWM provides multi-phase outputs, and these outputs can be

 

 

 

D

controlled to have a certain pattern sequence. In this way the force/torque of the

 

 

 

 

 

 

 

 

 

motor can be adjusted as desired. This makes the PWM function as a motor drive.DRAFT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRA

 

 

 

 

 

 

 

Sync_in Transfer_enable_in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VPB domain

 

 

 

 

 

 

 

PWM domain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

update

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWM

 

 

 

 

Match outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VPB system bus

 

 

 

PWM

Capture data

 

 

 

Counter,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

prescale

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

control

PWM counter value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

counter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

&

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

&

 

 

 

 

 

Capture inputs

 

 

 

 

 

 

 

 

 

registers

Config data

 

 

 

 

 

 

 

 

 

 

 

IRQ pwm

 

 

 

 

 

 

 

shadow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ’s

 

 

 

registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ capt_match

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Trap input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Carier inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sync_out Transfer_enable_out

Fig 10. PWM block diagram

The PWM block diagram in Figure 10 shows the basic architecture of each PWM. PWM functionality is split into two major parts, a VPB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective. The actual PWM and prescale counters are located in the PWM domain but system control takes place in the VPB domain.

The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM counter. The position of the rising and falling edges of the PWM outputs can be programmed individually. The prescale counter allows high system bus frequencies to be scaled down to lower PWM periods. Registers are available to capture the PWM counter values on external events.

Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references are related to the period of this clock. See Section 8.8 for information on generation of these clocks.

8.7.6.3Synchronizing the PWM counters

A mechanism is included to synchronize the PWM period to other PWMs by providing a sync input and a sync output with programmable delay. Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Section 8.7.2.1 for details of the connections of the PWM modules within the MSCSS in the LPC2917/19. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents About this document IntroductionGeneral description Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview …External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsPin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsFunctional description Serial peripheral interfaceUart clock description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configurationRGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin descriptionVIC clock description Limiting valuesVIC pin description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Package outline Contact information ContentsSoldering
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