NXP Semiconductors LPC2917, LPC2919 Reset Generation Unit RGU, Reset output configuration

Page 47

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

T

DRAFT

 

T

 

 

DRA

 

DRA

 

DR

 

F

 

 

F

 

 

8.8.5 Reset Generation Unit (RGU)

DRAFT DRAFT DRAF

 

 

 

 

 

 

8.8.5.1 Overview

 

DRAFT

DRAFT

The key features of the Reset Generation Unit (RGU) are:

 

• Reset controlled individually per subsystem

 

 

DRAFT

D

 

 

 

• Automatic reset stretching and release

 

 

 

 

DRA

 

 

 

 

 

 

• Monitor function to trace resets back to source

• Register write-protection mechanism to prevent unintentional resets

8.8.5.2 Description

The RGU controls all internal resets.

Each reset output is defined as a (combination of) reset input sources including the external reset input pins and internal power-on reset, see Table 25. The first five resets listed in this table form a sort of cascade to provide the multiple levels of impact that a reset may have. The combined input sources are logically OR-ed together so that activating any of the listed reset sources causes the output to go active.

Table 25. Reset output configuration

 

Reset Output

Reset Source

parts of the device reset when activated

 

POR_RST

power-on reset module

LP_OSC; is source for RGU_RST

 

 

 

 

 

RGU_RST

POR_RST, RSTN pin

RGU internal; is source for PCR_RST

 

 

 

 

 

PCR_RST

RGU_RST, WATCHDOG

PCR internal; is source for COLD_RST

 

 

 

 

 

COLD_RST

PCR_RST

parts with COLD_RST as reset source below

 

 

 

 

 

WARM_RST

COLD_RST

parts with WARM_RST as reset source below

 

 

 

 

 

SCU_RST

COLD_RST

SCU

 

 

 

 

 

CFID_RST

COLD_RST

CFID

 

 

 

 

 

FMC_RST

COLD_RST

embedded Flash-Memory Controller (FMC)

 

 

 

 

 

EMC_RST

COLD_RST

embedded SRAM-Memory Controller

 

 

 

 

 

SMC_RST

COLD_RST

external Static-Memory Controller (SMC)

 

 

 

 

 

GESS_A2V_RST

WARM_RST

GeSS AHB-to-VPB bridge

 

 

 

 

 

PESS_A2V_RST

WARM_RST

PeSS AHB-to-VPB bridge

 

 

 

 

 

GPIO_RST

WARM_RST

all GPIO modules

 

 

 

 

 

UART_RST

WARM_RST

all UART modules

 

 

 

 

 

TMR_RST

WARM_RST

all Timer modules in PeSS

 

 

 

 

 

SPI_RST

WARM_RST

all SPI modules

 

 

 

 

 

IVNSS_A2V_RST

WARM_RST

IVNSS AHB-to-VPB bridge

 

 

 

 

IVNSS_CAN_RST WARM_RST

all CAN modules including Acceptance filter

 

 

 

 

 

IVNSS_LIN_RST

WARM_RST

all LIN modules

 

 

 

 

 

MSCSS_A2V_RST

WARM_RST

MSCSS AHB to VPB bridge

 

 

 

 

 

MSCSS_PWM_RST

WARM_RST

all PWM modules

 

 

 

 

 

MSCSS_ADC_RST

WARM_RST

all ADC modules

 

 

 

 

 

MSCSS_TMR_RST

WARM_RST

all Timer modules in MSCSS

 

 

 

 

 

VIC_RST

WARM_RST

Vectored Interrupt Controller (VIC)

 

 

 

 

 

AHB_RST

WARM_RST

CPU and AHB Multilayer Bus infrastructure

 

 

 

 

LPC2917_19_1

 

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

47 of 68

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Contents Intended audience IntroductionGeneral description About this documentOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0LQFP144 pin SymbolPin Description Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash sector overview … Flash bridge wait-statesExternal memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionPin description TimerWatchdog timer clock description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsFunctional description Serial peripheral interfaceUart clock description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC pin description ADC block diagramAnalog to digital converter pins ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset output configuration Reset Generation Unit RGURGU pin description Power Management Unit PMURGU pins DRA PMU pin description Vectored interrupt controllerVIC clock description Limiting valuesVIC pin description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Package outline Contact information ContentsSoldering
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