NXP Semiconductors LPC2919, LPC2917 user manual UnitDRAFT

Page 56

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

 

 

 

 

 

 

 

 

 

T

DRAFT

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

DRA

 

DRA

 

DR

 

DD(CORE)

 

DD(OSC_PLL)

 

DD(IO)

 

 

DD(A3V3)

 

vj

 

F

 

F

 

V

= V

; V

 

 

 

 

DRAFT DRAFT

DRAF

 

 

 

= 2.7 V to 3.6 V; V

= 3.0 V to 3.6 V; T = −40

°C; all voltages are measured with

Table 31. Dynamic characteristics …continued

 

 

 

 

 

 

 

 

 

 

respect to ground; positive currents flow into the IC; unless otherwise specified.

 

 

UnitDRAFT

DRAFT

Symbol

 

Parameter

 

Conditions

 

Min

Typ

Max

fclk(sys)

 

System clock

 

 

 

 

10

-

80

MHz

DRAFT

D

Internal clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

frequency. See

 

 

 

 

 

 

 

 

 

 

DRA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tclk(sys)

 

System clock period.

 

 

 

12.5

-

100

ns

 

 

 

 

 

 

 

 

See Table 23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-Power Ring Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fref(RO)

 

RO reference

 

 

 

 

0.36

0.4

0.42

MHz

 

 

 

 

 

 

 

 

frequency.

 

 

 

 

 

 

 

 

 

 

 

 

 

tstartup

 

Start-up time.

 

At maximum frequency

-

6

100

μs

 

 

 

 

 

 

 

 

 

 

 

 

[2].

 

 

 

 

 

 

 

 

 

 

Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fi(osc)

 

Oscillator input

Maximum frequency is

10

-

80

MHz

 

 

 

 

 

 

 

 

frequency.

 

the clock input of an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

external clock source

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

applied to the Xin pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tstartup

 

Start-up time.

 

At maximum frequency.

-

500

-

μs

 

 

 

 

 

 

 

 

 

 

 

 

[2]

[3]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fi(PLL)

 

PLL input frequency.

 

 

 

10

-

25

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fo(PLL)

 

PLL output frequency.

 

 

 

10

-

160

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCO; direct mode.

156

-

320

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Analog-to-digital converter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fi(ADC)

 

ADC input frequency.

[4]

 

 

4

-

4.5

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fs(max)

 

Maximum sampling

fi(ADC) = 4.5 MHz;

 

 

 

 

 

 

 

 

 

 

 

 

rate.

 

 

 

fs = fi(ADC)/(n+1) with

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n = resolution

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

resolution 2 bit

-

-

1500

ksample/s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

resolution 10 bit

-

-

400

ksample/s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tconv

 

Conversion time.

In number of ADC clock

3

-

11

cycles

 

 

 

 

 

 

 

 

 

 

 

 

cycles.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In number of bits.

2

-

10

bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tinit

 

Initialization time.

 

 

 

-

-

150

μs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

twr(pg)

 

Page write time.

 

 

 

0.95

1

1.05

ms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ter(sect)

 

Sector erase time.

 

 

 

95

100

105

ms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tfl(BIST)

 

Flash word BIST time.

 

 

 

-

38

70

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tacc(clk)

 

clock access time

 

 

 

-

-

63.4

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tacc(addr)

 

address access time

 

 

 

-

-

60.3

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

external static memory controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ta(R)int

 

Internal read-access

 

 

 

-

-

20.5

ns

 

 

 

 

 

 

 

 

time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LPC2917_19_1

 

 

 

 

 

 

 

 

 

 

© NXP B.V. 2007. All rights reserved.

 

 

 

Preliminary data sheet

Rev. 1.01 — 15 November 2007

56 of 68

Page 55 Page 57
Image 56
Page 55 Page 57
Contents Introduction General descriptionAbout this document Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering optionsOrdering information Part optionsBlock diagram LPC2917/19 block diagramPinning information PinningPin description General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER2 MAT2 PWM TRAP1 TIMER2 MAT3 PWM TRAP0TIMER1 MAT0 EXTINT0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset, debug, test and power description Reset and power-up behaviorReset strategy Reset pinIeee 1149.1 interface pins Jtag boundary-scan test Power supply pins descriptionClocking strategy Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock and branch clock relationship Base clock and branch clock overviewBase clock Branch clock name Parts of the device clocked by This branch clockBlock description Flash memory controllerOverview Base clockDRA DescriptionFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview …External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External memory timing diagrams External memory controller pinsExternal static-memory controller pin description External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory Chip and feature identification General subsystemGeneral subsystem clock description System Control Unit SCUSymbol Direction Bit position Description Default Polarity Peripheral subsystemPeripheral subsystem clock description Event-router pin connectionsPin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin descriptionTimer clock description Timer pinsUart pins UARTsFunctional description Serial peripheral interfaceUart clock description SPI pins Modes of operationSPI pin description SPI clock descriptionGpio pins General-purpose I/O6.1 Overview Gpio pin descriptionCan pins Can gatewayLIN Global acceptance filterLIN controller pins Modulation and sampling control subsystemLIN pin description LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersTimers in the Mscss Master and slave modePWM pins PWM pin descriptionPower, clock and reset control subsystem Mscss timer-clock descriptionMscss timer 1 pin Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configurationRGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin descriptionVIC clock description Limiting valuesVIC pin description Thermal characteristics Static characteristics Static characteristicsSymbol Parameter Conditions Min Typ Max Input pins and I/O pins configured as inputAnalog-to-digital converter supply VDDA5V FSRINL LSBDynamic characteristics Power-up resetDynamic characteristics Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Soldering IntroductionThrough-hole mount packages Surface mount packagesVolume mm3 350 235 220 Lead-free process from J-STD-020C Temperature profiles for large and small componentsWave soldering SnPb eutectic process from J-STD-020C Package thickness mmPackage related soldering information Mounting Package1 Soldering method Wave Reflow2 DippingCPGA, Hcpga DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Package outline Contact information ContentsSoldering
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