NXP Semiconductors LPC2917, LPC2919 user manual Dynamic characteristics, Power-up reset, Pins

Page 55

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

 

 

 

 

 

 

 

 

 

T

DRAFT

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

DRA

 

DRA

 

DR

 

DD(CORE)

 

DD(OSC_PLL)

 

DD(IO)

 

DD(A3V3)

 

 

vj

 

F

 

 

F

 

V

= V

; V

 

= 3.0 V to 3.6 V; T

= -40 °C to +125

DRAFT DRAFT

DRAF

 

 

 

= 2.7 V to 3.6 V; V

 

°C; all voltages are

 

 

 

Table 30. Static characteristics …continued

 

 

 

 

 

 

 

 

 

 

 

measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]

 

DRAFTUnit

 

DRAFT

Symbol

 

Parameter

 

 

Conditions

 

Min

Typ

Max

 

Rs(xtal)

 

Crystal series resistance.

fosc = 10 MHz to 15 MHz

[5]

 

 

 

 

DRAFT

D

Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cxtal = 10 pF;

-

-

160

Ω

Cext = 18 pF

 

 

 

 

DRA

 

 

Cxtal = 20 pF;

 

-

-

60

Ω

 

 

Cext = 39 pF

 

 

 

 

 

 

 

fosc = 15 MHz to 20 MHz

[5]

 

 

 

 

 

 

Cxtal = 10 pF;

 

-

-

80

Ω

 

 

Cext = 18 pF

 

 

 

 

 

Ci

Input capacitance of

[9]

-

 

2

pF

 

XIN_OSC.

 

 

 

 

 

Power-up reset

 

 

 

 

 

 

 

 

 

 

 

 

Vtrip(high)

High trip-level voltage.

[6]

1.2

1.4

1.6

V

Vtrip(low)

Low trip-level voltage.

[6]

1.1

1.3

1.5

V

Vtrip(dif)

Difference between high

[6]

50

120

180

mV

 

and low trip-level

 

 

 

 

 

voltages.

[1]All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C on wafer level. Cased products are tested at Tamb = 25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover the specified temperature and power-supply voltage range.

[2]Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered down.

[3]For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input capacitance to ADC.

[4]This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or −38 mA. (drive LOW-level, shorted to VDD(IO)). The device will be damaged if multiple outputs are shorted.

[5]Cxtal is crystal load capacitance and Cext are the two external load capacitors.

[6]The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 μs before reset is de-asserted; VDD(CORE) must be below Vtrip(low) for 11 μs before internal reset is asserted.

[7]Not 5 V-tolerant when pull-up is on.

[8]For I/O Port 0, the maximum input voltage is defined by VI(ADC).

[9]This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results.

12. Dynamic characteristics

Table 31. Dynamic characteristics

VDD(CORE) = VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I/O pins

 

 

 

 

 

 

 

 

 

 

 

 

 

tTHL

HIGH-to-LOW

CL = 30 pF

4

-

13.8

ns

 

transition time.

 

 

 

 

 

tTLH

LOW-to-HIGH

CL = 30 pF

4

-

13.8

ns

 

transition time.

 

 

 

 

 

LPC2917_19_1

 

 

 

 

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

55 of 68

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Contents Intended audience IntroductionGeneral description About this documentARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Pin Description SymbolLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsUart clock description Serial peripheral interfaceFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline
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