NXP Semiconductors LPC2917, LPC2919 user manual Block diagram of the CGU

Page 43

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT		T
DRA	DRA DR
F	F
		DRAF
DRAFT DRAFT

Clock Source Bus			DRAFT DRAFT
LP_OSC			DRAFT DRAFT
			DRAFT	D
			DRAFT
Xtal	FDIV0	OUT 0	DRA
PLL	FDIV0	OUT 0
Oscilator
	FDIV1	OUT 1
	FDIV6	OUT 9
Frequency	Clock
Monitor	Detection
	DTL MMIO Interface

Fig 12. Block diagram of the CGU

There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See Figure 12.

LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer). To prevent the device from losing its clock source LP_OSC cannot be put into power-down. The crystal oscillator can be used as source for high-frequency clocks or as an external clock input if a crystal is not connected.

Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted.

Configuration of the CGU: For every output generator - generating the base clocks - a choice can be made from the primary and secondary clock generators according to Figure 13.

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

43 of 68

Image 43

Contents Intended audience IntroductionGeneral description About this documentARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Pin Description SymbolLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash sector overview … Flash bridge wait-statesExternal static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionWatchdog timer clock description TimerPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsUart clock description Serial peripheral interfaceFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftAnalog to digital converter pins ADC block diagramADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset output configuration Reset Generation Unit RGURGU pins Power Management Unit PMURGU pin description DRA PMU pin description Vectored interrupt controllerVIC pin description Limiting valuesVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Contact information Legal informationContents Soldering Contact information ContentsPackage outline