NXP Semiconductors LPC2917, LPC2919 Limiting values, VIC pin description, VIC clock description

Page 51

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T	DRAFT		T
DRA		DRA			DR
F			F
Interrupt-request masking is performed individually per interrupt target by comparing the				DRAF
priority level assigned to a specific interrupt request with a target-specific priorityDRAFT DRAFT
threshold. The priority levels are defined as follows:	DRAFT DRAFT
threshold. The priority levels are defined as follows:
• Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never					D
lead to an interrupt)		DRAFT
lead to an interrupt)
• Priority 1 corresponds to the lowest priority				DRA
• Priority 15 corresponds to the highest priority				DRA
• Priority 15 corresponds to the highest priority

Software interrupt support is provided and can be supplied for:

•Testing RTOS interrupt handling without using device-specific interrupt service routines

•Software emulation of an interrupt-requesting device, including interrupts

8.9.3VIC pin description

The VIC module in the LPC2917/19 has no external pins.

8.9.4VIC clock description

The VIC is clocked by CLK_SYS_VIC, see Section 7.2.2.

9.Limiting values

Table 28. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol	Parameter	Conditions		Min	Max	Unit
Supply pins

Ptot	Total power dissipation.		[1]	-	1	W
VDD(CORE)	Core supply voltage.			−0.5	+2.0	V
VDD(OSC_PLL)	Oscillator and PLL supply			−0.5	+2.0	V
	voltage.
VDD(ADC3V3)	3.3 V ADC supply voltage.			−0.5	+4.6	V
VDD(IO)	I/O digital supply voltage.			−0.5	+4.6	V
IDD	Supply current.	Average value per supply	[2]	-	98	mA
		pin.

ISS	Ground current.	Average value per ground	[2]	-	98	mA
		pin.
Input pins and I/O pins

VXIN_OSC	Voltage on pin XIN_OSC.			−0.5	+2.0	V
VXIN_RTC	Voltage on pin XIN_RTC.			−0.5	+2.0	V
VI(IO)	I/O input voltage.		[3][4][5]	−0.5	VDD(IO) + 3.0	V
VI(ADC)	ADC input voltage.	I/O port 0.	[4][5]	−0.5	VDD(ADC3V3) + 0.5	V

VVREFP	Voltage on pin VREFP.			−0.5	+3.6	V

VVREFN	Voltage on pin VREFN.			−0.5	+3.6	V

II(ADC)	ADC input current.	Average value per input pin.	[2]	-	35	mA

Output pins and I/O pins configured as output
LPC2917_19_1					© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

51 of 68

Image 51

Contents Intended audience IntroductionGeneral description About this documentNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Part options Ordering informationOrdering options Ordering informationLPC2917/19 block diagram Block diagramGeneral description Pinning informationPinning Pin descriptionLQFP144 pin assignment … Symbol Pin Description Function 0 defaultTIMER1 MAT1 EXTINT1 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT0 EXTINT0Symbol Pin DescriptionLQFP144 pin Reset pin Reset, debug, test and power descriptionReset and power-up behavior Reset strategyClock architecture Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clocking strategyLPC2917/19 LPC2917/19 block diagram, overview of clock areasThis branch clock Base clock and branch clock relationshipBase clock and branch clock overview Base clock Branch clock name Parts of the device clocked byBase clock Block descriptionFlash memory controller OverviewDescription DRAFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash sector overview … Flash bridge wait-states32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller clock description External memory timing diagramsExternal memory controller pins External static-memory controller pin descriptionWriting to external memory Reading from external memoryReading/writing external memory System Control Unit SCU Chip and feature identificationGeneral subsystem General subsystem clock descriptionEvent-router pin connections Symbol Direction Bit position Description Default PolarityPeripheral subsystem Peripheral subsystem clock descriptionTimer Watchdog timer clock descriptionPin description 3.3 Pin description 3.2 DescriptionUARTs Timer clock descriptionTimer pins Uart pinsSerial peripheral interface Uart clock descriptionFunctional description SPI clock description SPI pinsModes of operation SPI pin descriptionGpio pin description Gpio pinsGeneral-purpose I/O 6.1 OverviewGlobal acceptance filter Can pinsCan gateway LINLIN0/1 Txdl LIN controller pinsModulation and sampling control subsystem LIN pin descriptionModulation and sampling control subsystem block diagram Synchronization and trigger features of the MscssStart ADC conditions is valid Mscss clock description Mscss pin descriptionAnalog-to-digital converter DraftADC block diagram Analog to digital converter pinsADC pin description ADC clock description 6 PWMSynchronizing the PWM counters PWM block diagramPWM pin description Timers in the MscssMaster and slave mode PWM pinsPause pin for Mscss timer Power, clock and reset control subsystemMscss timer-clock description Mscss timer 1 pinPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU Number Name Frequency Description MHz CGU base clocksBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset output configuration Reset Generation Unit RGUPower Management Unit PMU RGU pinsRGU pin description DRA PMU pin description Vectored interrupt controllerLimiting values VIC pin descriptionVIC clock description Thermal characteristics Input pins and I/O pins configured as input Static characteristicsStatic characteristics Symbol Parameter Conditions Min Typ MaxLSB Analog-to-digital converter supplyVDDA5V FSR INLSymbol Parameter Conditions Min Typ Max Unit Dynamic characteristicsPower-up reset Dynamic characteristicsUnitDRAFT Can TXD pin Cycle-to-cycle jitter Peak-to-peak value Jitter SpecificationPackage outline SOT486-1 LQFP144 Package outlineSurface mount packages SolderingIntroduction Through-hole mount packagesSnPb eutectic process from J-STD-020C Package thickness mm Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components Wave solderingDBS, DIP, HDIP, RDBS, SDIP, SIL Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping CPGA, HcpgaMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Contact information Legal informationContents Contact information Contents SolderingPackage outline