NXP Semiconductors LPC2919 Block description, Flash memory controller, Overview, Base clock

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Base clock and branch clock overview …continued

NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

Table 7.

Base clock

BASE_MSCSS_CLK

Branch clock name

CLK_MSCSS_VPB

CLK_MSCSS_MTMR0

CLK_MSCSS_MTMR1

CLK_MSCSS_PWM0

CLK_MSCSS_PWM1

CLK_MSCSS_PWM2

CLK_MSCSS_PWM3

CLK_MSCSS_ADC1_V PB

T	DRAFT		T
DRA		DRA			DR
F			F
	DRAFT DRAF
Parts of the device clockedDRAFTby Remark			DRAFT
VPB side of the MSCSS	DRAFT		DRAFT
this branch clock
Timer 0 in the MSCSS		DRAFT			D
		DRAFT

Timer 1 in the MSCSS				DRA
PWM 0				DRA
PWM 0

PWM 0

PWM 0

PWM 0

VPB side of ADC 1

BASE_UART_CLK

BASE_SPI_CLK

BASE_TMR_CLK

BASE_ADC_CLK

BASE_CLK_TESTSHELL

CLK_MSCSS_ADC2_V VPB side of ADC 2

PB

CLK_UART0	UART 0 interface clock
CLK_UART1	UART 1 interface clock
CLK_SPI0	SPI 0 interface clock

CLK_SPI1	SPI 1 interface clock

CLK_SPI2	SPI 2 interface clock
CLK_TMR0	Timer 0 clock for counter part

CLK_TMR1	Timer 1 clock for counter part

CLK_TMR2	Timer 2 clock for counter part

CLK_TMR3	Timer 3 clock for counter part
CLK_ADC1	Control of ADC 1, capture sample
	result

CLK_ADC2	Control of ADC 2, capture sample
	result
CLK_TESTSHELL_IP

[1]This clock is always on (cannot be switched off for system safety reasons)

[2]In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock source. See Section 8.4 for details.

[3]In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock source. See Section 8.8 for details.

[4]The clock should remain activated when system wake-up on timer or UART is required.

8.Block description

8.1Flash memory controller

8.1.1Overview

The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two tasks:

•Providing memory data transfer

•Memory configuration via triggering, programming and erasing

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

14 of 68

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Contents About this document IntroductionGeneral description Intended audienceOn-chip flash memory system NXP SemiconductorsARM968E-S processor General FeaturesOn-chip static RAM Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1LQFP144 pin SymbolPin Description Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash layout Flash memory controller pin descriptionFlash memory controller clock description Flash bridge wait-states Flash sector overview …External memory-bank address bit description 32 bit Symbol Description System Address Bit FieldExternal static memory controller External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsPin description TimerWatchdog timer clock description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsFunctional description Serial peripheral interfaceUart clock description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC pin description ADC block diagramAnalog to digital converter pins 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerClock Generation Unit CGU Pcrss block diagramPCR subsystem clock description CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pin description PLL block diagramCGU pins Reset Generation Unit RGU Reset output configurationRGU pin description Power Management Unit PMURGU pins DRA Vectored interrupt controller PMU pin descriptionVIC clock description Limiting valuesVIC pin description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviation Description AbbreviationsAbbreviations list References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Package outline Contact information ContentsSoldering