NXP Semiconductors LPC2919, LPC2917 Pinning information, Pin description, General description

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NXP Semiconductors

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

6.Pinning information

6.1Pinning

144	109
1	108

LPC2917FBD144

LPC2919FBD144

36						73

		37		72		144PINS
						144PINS

Fig 2. Pin configuration for SOT486-1 (LQFP144)

T DRAFT	T
DRA	DRA DR
F	F
DRAFT DRAFT DRAF
DRAFT DRAFT
	DRAFT	D
	DRAFT
	DRA

6.2 Pin description

6.2.1General description

The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section.

6.2.2LQFP144 pin assignment

Table 3. LQFP144 pin assignment

Symbol Pin

TDO1

Description

Function 0 (default)	Function 1	Function 2	Function 3

IEEE 1149.1 test data out

P2.21	2	GPIO 2, pin 21	-	PWM2 CAP1	EXTBUS D19
P0.24	3	GPIO 0, pin 24	UART1 TxD	CAN1 TxD	SPI2 SCS0

P0.25	4	GPIO 0, pin 25	UART1 RxD	CAN1 RxD	SPI2 SDO

P0.26	5	GPIO 0, pin 26	-	-	SPI2 SDI

P0.27	6	GPIO 0, pin 27	-	-	SPI2 SCK

P0.28	7	GPIO 0, pin 28	-	TIMER0 CAP0	TIMER0 MAT0

P0.29	8	GPIO 0, pin 29	-	TIMER0 CAP1	TIMER0 MAT1

VDD(IO)	9	3.3 V power supply for I/O
P2.22	10	GPIO 2, pin 22	-	PWM2 CAP2	EXTBUS D20

P2.23	11	GPIO 2, pin 23	-	PWM3 CAP0	EXTBUS D21

P3.6	12	GPIO 3, pin 6	SPI0 SCS3	PWM1 MAT0	LIN1 TxD

P3.7	13	GPIO 3, pin 7	SPI2 SCS1	PWM1 MAT1	LIN1 RxD

P0.30	14	GPIO 0, pin 30	-	TIMER0 CAP2	TIMER0 MAT2

P0.31	15	GPIO 0, pin 31	-	TIMER0 CAP3	TIMER0 MAT3
LPC2917_19_1					© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

6 of 68

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Contents About this document IntroductionGeneral description Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview …32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsSerial peripheral interface Uart clock descriptionFunctional description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configurationPower Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin descriptionLimiting values VIC pin descriptionVIC clock description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact informationContents Contact information Contents SolderingPackage outline