NXP Semiconductors LPC2919, LPC2917 Analog-to-digital converter supply, VDDA5V FSR, Inl, Lsb, Dnl

Page 54

NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

 

 

 

 

 

 

 

T

DRAFT

 

 

 

T

 

 

 

 

 

 

 

 

 

 

DRA

 

DRA

 

DR

 

DD(CORE)

 

DD(OSC_PLL)

DD(IO)

DD(A3V3)

 

vj

 

F

 

 

 

F

 

V

= V

= 3.0 V to 3.6 V; T

= -40 °C to +125

DRAFT DRAFT

DRAF

 

 

; V

= 2.7 V to 3.6 V; V

 

°C; all voltages are

 

 

 

 

Table 30. Static characteristics …continued

 

 

 

 

 

 

 

 

 

 

 

measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]

 

DRAFTUnit

 

DRAFT

Symbol

 

Parameter

Conditions

Min

Typ

Max

 

ILIL

 

LOW-state input leakage

-

 

-

1

μA

DRAFT

D

 

 

 

current.

II(pd)

Pull-down input current. All port pins, VI = 3.3 V;

25

50

100

μA

 

VI = 5.5 V.

 

 

 

 

DRA

II(pu)

Pull-up input current.

All port pins, RESET_N, −25−50 −100 μA TRST_N, TDI,

JTAGSEL, TMS: VI = 0 V; VI > 3.6 V is not allowed.

Ci

Input capacitance.

 

[3] -

3

8

pF

Output pins and I/O pins configured as output

 

 

 

 

 

 

 

 

 

 

 

VO

Output voltage.

 

0

-

VDD(IO)

V

 

 

 

 

 

 

 

VOH

HIGH-state output

IOH = −4 mA

VDD(IO) – 0.4

-

-

V

 

voltage.

 

 

 

 

 

VOL

LOW-state output voltage. IOL = 4 mA

-

-

0.4

V

CL

Load capacitance.

 

-

-

25

pF

Analog-to-digital converter supply

 

 

 

 

 

 

 

 

 

 

 

 

VVREFN

Voltage on pin VREFN.

 

0

-

VVREFP − 2

V

VVREFP

Voltage on pin VREFP.

 

VVREFN + 2

-

VDD(A3V3)

V

VI(ADC)

ADC input voltage on

Port 0.

VVREFN

-

VVREFP

V

 

port 0 pins

 

 

 

 

 

Zi

Input impedance.

Between VREFN and

4.4

-

-

kΩ

 

 

VREFP

 

 

 

 

 

 

Between VREFN and

13.7

-

23.6

kΩ

 

 

VDD(A5V)

 

 

 

 

FSR

Full scale range.

 

2

-

10

bit

 

 

 

 

 

 

 

INL

Integral non-linearity.

 

−1

-

+1

LSB

 

 

 

 

 

 

 

DNL

Differential non-linearity.

 

−1

-

+1

LSB

 

 

 

 

 

 

 

Verr(offset)

Offset error voltage.

 

−20

-

+20

mV

Verr(FS)

Full-scale error voltage.

 

−20

-

+20

mV

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

54 of 68

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Contents About this document IntroductionGeneral description Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview …32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsSerial peripheral interface Uart clock descriptionFunctional description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configurationPower Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin descriptionLimiting values VIC pin descriptionVIC clock description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact informationContents Contact information Contents SolderingPackage outline
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