NXP Semiconductors LPC2919 Functional description, Reset, debug, test and power description

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NXP Semiconductors

Table 3.	LQFP144 pin assignment …continued
Symbol	Pin	Description

DRAFT	D	D		AFT
DRAFT	RAFT	RAFT AFT		AFT
			DR	DR

DLPC2917/19
ARM9 microcontrollerRAFT	withDRAFTCANDRAFTand LINDRAFT
	T DRAFT	T
DRA		DRA DR
	F	F
	DRAFT DRAFT DRAF

		Function 0 (default)	Function 1
P0.18	132	GPIO 0, pin 18	ADC2 IN2
P0.19	133	GPIO 0, pin 19	ADC2 IN3
P3.4	134	GPIO 3, pin 4	TIMER3 MAT2
P3.5	135	GPIO 3, pin 5	TIMER3 MAT3
P2.18	136	GPIO 2, pin 18	-
P2.19	137	GPIO 2, pin 19	-
P0.20	138	GPIO 0, pin 20	ADC2 IN4
P0.21	139	GPIO 0, pin 21	ADC2 IN5
P0.22	140	GPIO 0, pin 22	ADC2 IN6
VSS(IO)	141	ground for I/O

Function 2

PWM2 MAT0

PWM2 MAT1

PWM2 MAT4

PWM2 MAT5

PWM1 CAP1

PWM1 CAP2

PWM2 MAT2

PWM2 MAT3

PWM2 MAT4

Function 3	DRAFT DRAFT

EXTBUS A14		DRAFT	D
EXTBUS A15

CAN1 TxD		DRA
CAN1 RxD

EXTBUS D16

EXTBUS D17

EXTBUS A16

EXTBUS A17

EXTBUS A18

P0.23	142	GPIO 0, pin 23	ADC2 IN7
P2.20	143	GPIO 2, pin 20	-
TDI	144	IEEE 1149.1 data in, pulled up internally.

PWM2 MAT5	EXTBUS A19
PWM2 CAP0	EXTBUS D18

7.Functional description

7.1Reset, debug, test and power description

7.1.1Reset and power-up behavior

The LPC2917/19 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See Section 11 for trip levels of the internal power-up reset circuit1. See Section 12 for characteristics of the several start-up and initialization times. Table 4 shows the reset pin.

Table 4.	Reset pin
Symbol	Direction	Description
RSTN	in	external reset input, active LOW; pulled up internally

At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment.

7.1.2Reset strategy

The LPC2917/19 contains a central module, the Reset Generator Unit (RGU) in the Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset signals towards the peripheral modules. The RGU provides individual reset control as well as the monitoring functions needed for tracing a reset back to source.

1.Only for 1.8 V power sources

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents About this document IntroductionGeneral description Intended audienceARM968E-S processor NXP SemiconductorsOn-chip flash memory system On-chip static RAM FeaturesGeneral Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1Pin Description SymbolLQFP144 pin Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash memory controller clock description Flash memory controller pin descriptionFlash layout Flash bridge wait-states Flash sector overview …External static memory controller 32 bit Symbol Description System Address Bit FieldExternal memory-bank address bit description External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsWatchdog timer clock description TimerPin description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsUart clock description Serial peripheral interfaceFunctional description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterAnalog to digital converter pins ADC block diagramADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerPCR subsystem clock description Pcrss block diagramClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description CGU pins PLL block diagramCGU pin description Reset Generation Unit RGU Reset output configurationRGU pins Power Management Unit PMURGU pin description DRA Vectored interrupt controller PMU pin descriptionVIC pin description Limiting valuesVIC clock description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations list AbbreviationsAbbreviation Description References Revision history Document ID Release date Data sheet statusRevision history Legal information Contact informationContents Soldering Contact information ContentsPackage outline