NXP Semiconductors LPC2919 Can gateway, Lin, Global acceptance filter, Can pin description

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NXP Semiconductors

DRAFT

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D

 

AFT

RAFT

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DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

 

 

DRA

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F

 

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8.5

CAN gateway

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DRAFT DRAFT DRAF

8.5.1

Overview

 

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Controller Area Network (CAN) is the definition of a high-performance communication

 

 

D

 

protocol for serial data communication. The two CAN controllers in the LPC2917/19

DRAFT

 

 

 

provide a full implementation of the CAN protocol according to the CAN specification

 

 

 

 

DRA

 

version 2.0B. The gateway concept is fully scalable with the number of CAN controllers,

 

and always operates together with a separate powerful and flexible hardware acceptance filter.

The key features are:

• Supports 11-bit as well as 29-bit identifiers

• Double receive buffer and triple transmit buffer

• Programmable error-warning limit and error counters with read/write access

• Arbitration-lost capture and error-code capture with detailed bit position

• Single-shot transmission (i.e. no re-transmission)

• Listen-only mode (no acknowledge; no active error flags)

• Reception of ‘own’ messages (self-reception request)

• Full CAN mode for message reception

8.5.2 Global acceptance filter

The global acceptance filter provides look-up of received identifiers - called acceptance filtering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table memory, in which software maintains one to five sections of identifiers. The CAN ID look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024 standard frame identifiers (SFF) or 512 extended frame identifiers (EFF) or a mixture of both types. It is also possible to define identifier groups for standard and extended message formats.

8.5.3 CAN pin description

The two CAN controllers in the LPC2917/19 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2917/19. Table 18 shows the CAN pins (x runs from 0 to 1).

Table 18. CAN pins

Symbol

Direction

Description

CANx TXDC

out

CAN channel x transmit data output

 

 

 

CANx RXDC

in

CAN channel x receive data input

 

 

 

8.6LIN

8.6.1Overview

The LPC2917/19 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2.0 master controllers with additional support for sync break generation and with hardware implementation of the LIN protocol according to spec 2.0.

The key features are:

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

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Contents About this document IntroductionGeneral description Intended audienceNXP Semiconductors ARM968E-S processorOn-chip flash memory system Features On-chip static RAMGeneral Ordering information Ordering informationOrdering options Part optionsBlock diagram LPC2917/19 block diagramPin description Pinning informationPinning General descriptionSymbol Pin Description Function 0 default LQFP144 pin assignment …TIMER1 MAT0 EXTINT0 TIMER2 MAT2 PWM TRAP1TIMER2 MAT3 PWM TRAP0 TIMER1 MAT1 EXTINT1Symbol Pin DescriptionLQFP144 pin Reset strategy Reset, debug, test and power descriptionReset and power-up behavior Reset pinClocking strategy Ieee 1149.1 interface pins Jtag boundary-scan testPower supply pins description Clock architectureLPC2917/19 block diagram, overview of clock areas LPC2917/19Base clock Branch clock name Parts of the device clocked by Base clock and branch clock relationshipBase clock and branch clock overview This branch clockOverview Block descriptionFlash memory controller Base clockDRA DescriptionFlash memory controller pin description Flash memory controller clock descriptionFlash layout Flash bridge wait-states Flash sector overview …32 bit Symbol Description System Address Bit Field External static memory controllerExternal memory-bank address bit description External static-memory controller pin description External memory timing diagramsExternal memory controller pins External static-memory controller clock descriptionReading from external memory Writing to external memoryReading/writing external memory General subsystem clock description Chip and feature identificationGeneral subsystem System Control Unit SCUPeripheral subsystem clock description Symbol Direction Bit position Description Default PolarityPeripheral subsystem Event-router pin connectionsTimer Watchdog timer clock descriptionPin description 3.2 Description 3.3 Pin descriptionUart pins Timer clock descriptionTimer pins UARTsSerial peripheral interface Uart clock descriptionFunctional description SPI pin description SPI pinsModes of operation SPI clock description6.1 Overview Gpio pinsGeneral-purpose I/O Gpio pin descriptionLIN Can pinsCan gateway Global acceptance filterLIN pin description LIN controller pinsModulation and sampling control subsystem LIN0/1 TxdlSynchronization and trigger features of the Mscss Modulation and sampling control subsystem block diagramStart ADC conditions is valid Mscss pin description Mscss clock descriptionDraft Analog-to-digital converterADC block diagram Analog to digital converter pinsADC pin description 6 PWM ADC clock descriptionPWM block diagram Synchronizing the PWM countersPWM pins Timers in the MscssMaster and slave mode PWM pin descriptionMscss timer 1 pin Power, clock and reset control subsystemMscss timer-clock description Pause pin for Mscss timerPcrss block diagram PCR subsystem clock descriptionClock Generation Unit CGU CGU base clocks Number Name Frequency Description MHzBlock diagram of the CGU Structure of the clock generation scheme PLL functional description PLL block diagram CGU pinsCGU pin description Reset Generation Unit RGU Reset output configurationPower Management Unit PMU RGU pinsRGU pin description DRA Vectored interrupt controller PMU pin descriptionLimiting values VIC pin descriptionVIC clock description Thermal characteristics Symbol Parameter Conditions Min Typ Max Static characteristicsStatic characteristics Input pins and I/O pins configured as inputINL Analog-to-digital converter supplyVDDA5V FSR LSBDynamic characteristics Dynamic characteristicsPower-up reset Symbol Parameter Conditions Min Typ Max UnitUnitDRAFT Jitter Specification Can TXD pin Cycle-to-cycle jitter Peak-to-peak valuePackage outline Package outline SOT486-1 LQFP144Through-hole mount packages SolderingIntroduction Surface mount packagesWave soldering Volume mm3 350 235 220 Lead-free process from J-STD-020CTemperature profiles for large and small components SnPb eutectic process from J-STD-020C Package thickness mmCPGA, Hcpga Package related soldering informationMounting Package1 Soldering method Wave Reflow2 Dipping DBS, DIP, HDIP, RDBS, SDIP, SILMounting Abbreviations Abbreviations listAbbreviation Description References Document ID Release date Data sheet status Revision historyRevision history Legal information Contact informationContents Contact information Contents SolderingPackage outline
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