Compaq EV67 manuals
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Compaq EV67 Specifications
356 pages 3.99 Mb
2 Alpha 21264/EV67 Hardware Reference Manual3 Table of Contents17 Preface25 Introduction29 Internal Architecture69 Hardware Interface89 Cache and External Interfaces143 Internal Processor Registers185 Privileged Architecture Library Code209 Initialization and Configuration229 Error Detection and Error Handling241 Electrical Data251 Thermal Management259 Testability and Diagnostics267 A285 B21264/EV67 Boundary-Scan RegisterThis appendix contains the BSDL description of the 21264/EV67 boundary-scan regis- ter. B.1 Boundary-Scan RegisterB.1.1 BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register 299 DPALcode Restrictions and GuidelinesD.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper 306 D.2 Restriction 2 : No Multiple Writers to IPRs in S ame Scoreboard GroupD.3 Restriction 4 : No Writers and Readers to IPRs in Same Score- board GroupGuideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write 307 D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read- Modify-WriteD.5 Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ ITOFRestriction 9 : PALmode Istream Address Ranges 308 D.6 Restriction 9 : PALmode Istream Address RangesD.7 Restriction 10: Duplicate IPR Mode BitsRestriction 11: Ibox IPR Update Synchronization 309 D.8 Restriction 11: Ibox IPR Update Synchronization D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM D.10 Restriction 13 : DTB Fill Flow Collision D.11 Restriction 14 : HW_RET Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1 311 D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1 D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock FlagRestriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, 312 D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAPD.21 Restriction 25: HW_MTPR ITB_IA After Reset D.22 Guideline 26: Conditional Branches in PALcode Restriction 27: Reset of Force-Fail Lock Flag State in PALcode 313 D.23 Restriction 27: Reset of Force-Fail Lock Flag State in PALcode D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR 315 D.27 Restriction 31 : I_CTL[VA_48] UpdateD.28 Restriction 32 : PCTR_CTL UpdateRestriction 33 : HW_LD Physical/Lock Use 316 D.29 Restriction 33 : HW_LD Physical/Lock UseD.30 Restriction 34 : Writing Multiple ITB Entries in the Same PAL- code Flow D.31 Guideline 35 : HW_INT_CLR Update D.32 Restriction 36 : Updating I_CTL[SDE] D.33 Restriction 37 : Updating VA_CTL[VA_48] D.34 Restriction 38 : Updating PCTR_CTLGuideline 39: Writing Multiple DTB Entries in the Same PAL Flow 317 D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL FlowD.36 Restriction 40: Scrubbing a Single-Bit Error 320 D.42 Restriction 46: Avoiding Live locks in Speculative Load CRD HandlersD.43 Restriction 47: Cache Eviction for Single-Bit Cache Errors 323 E
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