Compaq 21264, EV67 specifications Floating-Point Control Register

Floating-Point Control Register

Table 2–14 Floating-Point Control Register Fields (Continued)

Name Extent Type Description

UNFD	[61]	RW	Underflow Disable. The 21264/EV67 hardware cannot generate IEEE compli-
			ant denormal results. UNFD is used in conjunction with UNDZ as follows:
				UNFD	UNDZ	Result
			0		X	Underflow trap.
			1		0	Trap to supply a possible denormal result.
			1		1	Underflow trap suppressed. Destination is written with a
						true zero (+0.0).
UNDZ	[60]	RW	Underflow to zero. When UNDZ is set together with UNFD, underflow traps
			are disabled and the 21264/EV67 places a true zero in the destination register.
			See UNFD, above.
DYN	[59:58]	RW	Dynamic rounding mode. Indicates the rounding mode to be used by an IEEE
			floating-point instruction when the instruction specifies dynamic rounding
			mode:
				Bits	Meaning
			00		Chopped
			01		Minus infinity
			10		Normal
			11		Plus infinity
IOV	[57]	RW	Integer overflow. An integer arithmetic operation or a conversion from float-
			ing-point to integer overflowed the destination precision.
INE	[56]	RW	Inexact result. A floating-point arithmetic or conversion operation gave a result
			that differed from the mathematically exact result.
UNF	[55]	RW	Underflow. A floating-point arithmetic or conversion operation gave a result
			that underflowed the destination exponent.
OVF	[54]	RW	Overflow. A floating-point arithmetic or conversion operation gave a result that
			overflowed the destination exponent.
DZE	[53]	RW	Divide by zero. An attempt was made to perform a floating-point divide with a
			divisor of zero.
INV	[52]	RW	Invalid operation. An attempt was made to perform a floating-point arithmetic
			operation and one or more of its operand values were illegal.
OVFD	[51]	RW	Overflow disable. If this bit is set and a floating-point arithmetic operation gen-
			erates an overflow condition, then the appropriate IEEE nontrapping result is
			placed in the destination register and the trap is suppressed.
DZED	[50]	RW	Division by zero disable. If this bit is set and a floating-point divide by zero is
			detected, the appropriate IEEE nontrapping result is placed in the destination
			register and the trap is suppressed.
INVD	[49]	RW	Invalid operation disable. If this bit is set and a floating-point operate generates
			an invalid operation condition and 21264/EV67 is capable of producing the

correct IEEE nontrapping result, that result is placed in the destination register and the trap is suppressed.

Alpha 21264/EV67 Hardware Reference Manual Internal Architecture 2–37