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Compaq EV67, 21264 specifications 8PALcode Restrictions and Guidelines

Models: 21264 EV67

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Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group

br	r31,palbase_init
palbase_init:
br	r0, br60		/* r0 <- current location */
br60: lda	r1, (EntryPoint-br60)(r0) /* r1 <- location of codebase */
mtpr	r1, EV6__PAL_BASE /* set up pal_base register */
bis	r31, 2, r0
mtpr	r0, EV6__VA_CTL
bis	r31, 8, r0
mtpr	r0, EV6__M_CTL
br	r0, jmp0
jmp0: addq	r0, (jmp1-jmp0+1), r0
hw_rets/jmp(r0)
jmp1:
lda	r1,	1(r31)	/* r1 <- cc_ctl enable bit */
sll	r1,	32, r1
mtpr	r1, EV6__CC_CTL		/* Enable/clear the cycle counter. */

/*

**Now initialize the dcache to allow the

**minidebugger so save gpr’s

*/

D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group

For convenience of implementation, only one explicit writer (HW_MTPR) to IPRs that are in the same group can appear in the same fetch block (octaword-aligned octaword). Multiple explicit writers to IPRs that are not in the same scoreboard group can appear. If this restriction is violated, the IPR readers might not see the in-order state. Also, the IPR might ultimately end up with a bad value.

D.3 Restriction 4 : No Writers and Readers to IPRs in Same Score- board Group

This restriction is made for the convenience of microprocessor implementation.

An explicit reader of an IPR in a particular scoreboard group cannot follow an explicit writer (HW_MTPR) to an IPR in that same scoreboard group within one fetch block (octaword-aligned octaword). Also within one fetch block, an implicit reader of an IPR in a particular scoreboard group cannot follow an explicit writer (HW_MTPR) to an IPR in that scoreboard group. This restriction covers writes to DTB_PTE or DTB_TAG followed by LD, ST, or any memory operation, including all types of JMP instructions and HW_RET instructions that do not have the STALL bit set.

D–8PALcode Restrictions and Guidelines

Alpha 21264/EV67 Hardware Reference Manual

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Compaq EV67, 21264 specifications 8PALcode Restrictions and Guidelines

Contents

Hardware Reference Manual Revision/Update InformationAlpha 21264A Microprocessor DS-0028A-TEAlpha 21264/EV67 Hardware Reference Manual Table of Contents Hardware Interface Cache and External InterfacesInternal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr MtfpcrElectrical Data Error Detection and Error HandlingTestability and Diagnostics Thermal ManagementAlpha Instruction Set 21264/EV67 Boundary-Scan Register21264/EV67-to-Bcache Pin Interconnections Glossary IndexFigures Xii Tables Xiv VDD Idcpower Page Content PrefaceAudience Documentation Included by Reference Terminology and Conventions For exampleAbbreviations Addresses W1CW1S Aligned and UnalignedDo Not Care Signal NamesData Units ExternalUndefined Do not care. a capital X represents any valid value Page Introduction ArchitectureIntroduction Integer Data Types ArchitectureAddressing Floating-Point Data Types21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features21264/EV67 Microprocessor Features Internal Architecture 21264/EV67 MicroarchitectureInternal Architecture Instruction Fetch, Issue, and Retire Unit 21264/EV67 MicroarchitectureVirtual Program Counter Logic 21264/EV67 Block Diagram Branch PredictorLocal Predictor Global PredictorChoice Predictor Instruction-Stream Translation BufferInteger Issue Queue Instruction Fetch LogicRegister Rename Maps Floating-Point Issue Queue HwretInteger Execution Unit Exception and Interrupt LogicRetire Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0Floating-Point Execution Unit 10Internal ArchitectureExternal Cache and System Interface Unit Onchip Caches21264/EV67 contains two onchip primary-level caches Memory Reference Unit Data Cache12Internal Architecture Srom Interface Pipeline OrganizationPipeline Organization Miss address file MAF Dstream translation buffer DTBStage 0 Instruction Fetch Stage 1 Instruction Slot14Internal Architecture Stage 3 Issue Stage 2 MapPipeline Aborts Instruction Issue RulesInstruction Issue Rules Ebox and Fbox pipelines begin executionInstruction Issue Rules Instruction Group Definitions Instruction Name, Pipeline, and TypesITOFS, ITOFF, Itoft Ebox SlottingFTOIS, Ftoit Instruction Group Definitions and Pipeline UnitU U L E L U E E L L E U Hwmfpr Instruction Issue Rules Instruction LatenciesInstruction Class Latency in Cycles 20Internal ArchitectureInstruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Floating-Point Divide/Square Root Early Retire Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 BSR/JSRPrefetch with Modify Intent LDS Instruction Load Instructions to R31 and F31Load Instructions to R31 and F31 Instructions Retired Without ExecutionLoad Hit Speculation Special Cases of Alpha Instruction ExecutionPrefetch with the LDxL / STxC Instruction Sequence 24Internal ArchitectureSpecial Cases of Alpha Instruction Execution Pipeline Timing for Integer Load InstructionsFloating-Point Store Instructions Cmov Instruction26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions 2 I/O Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging28Internal Architecture 4 I/O Address Space Store Instructions 8shows some of the following rulesRules for I/O Address Space Store Instruction Data Merging MAF Memory Address Space Merging Rules MAF Memory Address Space Merging RulesInstruction Ordering MAF Merging RulesMbox Order Traps Replay TrapsReplay Traps 10 Memory Reference OrderingOther Mbox Replay Traps 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Memory Barrier MB/WMB/TB Fill FlowMB Instruction Processing 12 TB Fill Flow Example Sequence WMB Instruction ProcessingTB Fill Flow 34Internal Architecture13 TB Fill Flow Example Sequence Performance Measurement Support-Performance Counters Performance Measurement Support-Performance CountersFloating-Point Control Register Floating-point control register Fpcr is shown in FigureFloating-Point Control Register Amask Amask and Implver Instruction ValuesAmask and Implver Instruction Values ImplverDesign Examples Design Examples13 Typical Multiprocessor Configuration 40Internal Architecture21264/EV67 Microprocessor Logic Symbol Hardware InterfaceHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic SymbolSignal Pin Types Definitions 21264/EV67 Signal Names and Functions21264/EV67 Signal Names and Functions 21264/EV67 Signal DescriptionsDcokh Pllvdd 21264/EV67 Signal Descriptions by Function TestStatHSysVref Domain SysAddInL140 Pin List Sorted by Signal Name Pin AssignmentsPin Assignments AC1 10Hardware Interface PllvddAA5 Pin List Sorted by PGA Location 12Hardware InterfaceSysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware InterfaceMechanical Specifications Mechanical Specifications21264/EV67 Packaging 21264/EV67 Packaging18Hardware Interface 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Introduction to the External InterfacesCache and External Interfaces Introduction to the External Interfaces System Interface 21264/EV67 System and Bcache InterfacesPhysical Address Considerations Commands and AddressesPhysical Address Considerations Second-Level Cache Bcache InterfaceECB I/O MB/WMBPhysical Address Considerations Bcache Structure Bcache Interface SignalsBcache Structure System Duplicate Tag StoresVictim Data Buffer Victim Data BufferCache Coherency Cache Coherency Basics2lists the cache block states supported by the 21264/EV67 Cache CoherencyCache Block States 21264/EV67-Supported Cache Block StatesCache Block State Transitions System Responses to 21264/EV67 CommandsCache Block State Transitions 10Cache and External InterfacesCache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Internal Eviction of LDxL Blocks Liveness and FairnessSystem Port System Port16Cache and External Interfaces System Port Pins System Port PinsProgram Values for Data-Sample/Drive CSRs System Port Programming the System Interface ClocksProgramming Values for System Interface Clocks 18Cache and External Interfaces3 21264/EV67-to-System Commands Bank Interleave on Cache Block Boundary ModeForwarded Clocks and Frame Clock Ratio 12 21264/EV67-to-System Command Fields Definitions Hit Mode11 Page Hit Mode of Operation 12describes the field definitions for Tables 4-10and14 21264/EV67-to-System Commands Descriptions 4 21264/EV67-to-System Commands Descriptions14describes the 21264/EV67-to-system commands 13 Maximum Physical Address for Short Bus Format22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 17 21264/EV67 ProbeResponse Command ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 24Cache and External InterfacesSysAck and 21264/EV67-to-System Commands Flow Control 18describes the ProbeResponse command fields18 ProbeResponse Fields Descriptions 19 System-to-21264/EV67 Probe Commands System-to-21264/EV67 CommandsProbe Commands Four Cycles RVB RPB22lists the next cache block state selected by Probe20 20 System-to-21264/EV67 Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 21 Data Movement Selection by Probe43Data Transfer Commands Two Cycles 23 Data Transfer Command Format28Cache and External Interfaces 24describes the SysDc40 field 24 SysDc40 Field DescriptionData Movement In and Out of the 21264/EV67 8.1 21264/EV67 Clock Basics30Cache and External Interfaces Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External Interfaces26shows four example configurations and shows their use 26 Cbox CSR SYSDCDELAY40 ExamplesFast Data Disable Mode SysDataInValidL 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL 34Cache and External InterfacesSysDataOutValidL SysFillValidLData Wrapping 28 Data Wrapping Rules36Cache and External Interfaces 30defines the interleaved scheme for the wrap order 29 System Wrap and Deliver Data30 Wrap Interleave Order 31 Wrap Order for Double-Pumped Data Transfers Nonexistent Memory Processing31defines the wrap order for double-pumped data transfers 38Cache and External Interfaces21264/EV67 Command NXM Address System/21264/EV67 Response 10.1 21264/EV67 Commands and System Probes Ordering of System Port Transactions40Cache and External Interfaces System Port Bcache Port Bcache PortBcache Port Pins 36 Bcache Port Pins35 Range of Maximum Bcache Clock Ratios Bcache Clocking 44Cache and External Interfaces37 BCCPUCLKDELAY10 Values 38 BCCLKDELAY10 ValuesSetting the Period of the Cache Clock 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External InterfacesBcache Transactions 41 Data-Sample/Drive Cbox CSRsBcache Data Read and Tag Read Transactions Bcache Data Write Transactions 48Cache and External InterfacesFor example, in single-data mode When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio Dual-data mode, bcfrm is twice the ratio50Cache and External Interfaces Relationship Between Read-to-Write Bcrdwrbubbles and rdwr Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd BcAddH23444lists the combination of control pin assertion for 46 Control Pin Assertion for Ramtype C 47 Control Pin Assertion for Ramtype DBcDataInClkH and BcTagInClkH Disabling the Bcache for Debugging InterruptsInterrupts Bcache Banking 54Cache and External InterfacesInternal Processor Registers Internal Processor RegistersMbox IPRs Cycle Counter Register CC Ebox IPRsEbox IPRs Cycle Counter Control Register Ccctl2describes the Ccctl register fields Virtual Address Register VAVirtual Address Control Register Vactl Cycle Counter Control Register Fields DescriptionVirtual Address Control Register Fields Description Virtual Address Format Register Vaform3describes the virtual address control register fields VAFORM32ITB Tag Array Write Register Itbtag Ibox IPRsIbox IPRs ITB PTE Array Write Register ItbpteITB Invalidate All Process ASM=0 Register Itbiap ITB Invalidate All Register ItbiaITB Invalidate Single Register Itbis 4describes the ProfileMe PC register fields Ibox IPRs ProfileMe PC Register PmpcException Address Register Excaddr ProfileMe PC Fields DescriptionInterrupt Enable and Current Processor Mode Register Iercm 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equalsSoftware Interrupt Request Register Sirr Iercm Register Fields Description10Internal Processor Registers Interrupt Summary Register Isum 6describes the software interrupt request register fieldsSoftware Interrupt Request Register Fields Description Interrupt Summary Register Fields Description Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields 12Internal Processor RegistersHardware Interrupt Clear Register Fields Description Exception Summary Register Excsum8describes the hardware interrupt clear register fields Mchkd W1C9describes the exception summary register fields Exception Summary Register Fields Description14Internal Processor Registers 10describes the PAL base register fields PAL Base Register PalbaseIbox Control Register Ictl 10 PAL Base Register Fields Description11describes the Ibox control register fields 11 Ibox Control Register Fields Description16Internal Processor Registers STWAIT64K SingleissuehMchken PCT1ENIbox Status Register Istat Spce18Internal Processor Registers MIS 12describes the Ibox status register fields12 Ibox Status Register Fields Description TRP20Internal Processor Registers Icache Flush ASM Register Icflushasm Sleep Mode Register SleepIbox IPRs Icache Flush Register Icflush Clear Virtual-to-Physical Map Register Clrmap14describes the process context register fields 14 Process Context Register Fields Description22Internal Processor Registers Performance Counter Control Register Pctrctl FPEPpce 15describes the performance counter control register fields 15 Performance Counter Control Register Fields Description24Internal Processor Registers DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 Mbox IPRsMbox IPRs 16 Performance Counter Control Register Input Select FieldsDTB Alternate Processor Mode Register Dtbaltmode 26Internal Processor RegistersDstream TB Invalidate All Register Dtbia 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,118 Memory Management Status Register Fields Description Memory Management Status Register Mmstat18describes the memory management status register fields 28Internal Processor RegistersMbox Control Register Mctl ForACV 19describes the Mbox control register fields Erences to superpages result in access violationsDcache Control Register Dcctl 19 Mbox Control Register Fields DescriptionDcache Status Register Dcstat 20describes the Dcache control register fields20 Dcache Control Register Fields Description 21describes the Dcache status register fields Cbox CSRs and IPRsCbox CSRs and IPRs 21 Dcache Status Register Fields DescriptionCbox Writeonce Chain Description Cbox CSRs and IPRs Cbox Data Register CdataCbox Shift Register Cshft 22 describes the Cbox data register fields24 Cbox Writeonce Chain Order 34Internal Processor RegistersMboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 Skewedfillmode36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers25describes the Cbox Writemany chain order from LSB to MSB 25 Cbox Writemany Chain OrderSetdirtyenable = Bcbankenable = 40Internal Processor RegistersCbox CSRs and IPRs Cbox Read Register IPR Description 26 Cbox Read IPR Fields DescriptionPage Privileged Architecture Library Code PALcode DescriptionPrivileged Architecture Library Code PALmode Environment PALmode EnvironmentRequired PALcode Function Codes Required PALcode Function CodesOpcodes Reserved for PALcode Hwld Instruction3describes the Hwld instruction fields Opcodes Reserved for PALcodeHwst Instruction Hwld Instruction Fields DescriptionsHwret Instruction 4describes the Hwst instruction fieldsHwst Instruction Fields Descriptions Hwret Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hint6describes the Hwmfpr and Hwmtpr instructions fields Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms Hwmfpr and Hwmtpr Instructions Fields DescriptionsHardware Structure of Explicitly Written IPRs IPR Access Ordering Paired Instruction Fetch Order10Privileged Architecture Library Code PALshadow Registers PALcode Emulation of the FpcrPALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry LocationsDTB Fill Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows 14Privileged Architecture Library CodeWr Data Tb missWr PTE LD-PTE, write TB ITB Fill 16Privileged Architecture Library CodePerformance Counter Support Performance Counter SupportAggregate Mode Precautions General PrecautionsAggregate Mode Programming Guidelines IPRs Used for Performance Counter SupportPctrctl SL0 10 Aggregate Mode Returned IPR ContentsOperation SL1ProfileMe Mode Programming Guidelines 11shows the counter modes that are used with Aggregate modeThis input counts Mbox replay traps 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library CodeProfileMe Counting Mode Description Cycle counting Inum retire delay cycles14 ProfileMe Mode Pctrctl Input Select Fields 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 24Privileged Architecture Library Code21264/EV67 Reset State Machine Major Operations Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins ConstraintsPower Sequencing and Reset State for Signal Pins Signal Pin Reset StateClock Forwarding and System Clock Ratio Configuration PllvddPin Signal Names and Initialization State PLLPLL Ramp Up BiST and Srom Load and the TestStatH PinClock Forward Reset and System Interface Initialization Power-Up Flow Signals and Their ConstraintsFault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode FlowEffect on IPRs After Transition Through Sleep Mode 10Initialization and ConfigurationSignals and Constraints for the Sleep Mode Sequence Warm Reset FlowWarm Reset Flow Effect on IPRs After Warm ResetArray Initialization Initialization Mode Processing12Initialization and Configuration Array InitializationInitialization Mode Processing EVICTENABLE014Initialization and Configuration Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State External Interface InitializationInternal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Ieee 1149.1 Test Port ResetReset State Machine 16Initialization and ConfigurationReset State Machine 11 21264/EV67 Reset State Machine State Descriptions18Initialization and Configuration Differential Reference Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description PLL Output ClocksPower-Up/Reset Clocking 20Initialization and ConfigurationError Detection and Error Handling 21264/EV67 Error Detection MechanismsError Detection and Error Handling Dcache Tag Parity Error Data Error Correction CodeIcache Data or Tag Parity Error Data Error Correction CodeDcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Store Second Error Dcache Store Second ErrorDcache Duplicate Tag Parity Error Store Instruction Quadword or SmallerBcache Tag Parity Error Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Icache Fill from BcacheBcache Victim Read Bcache Victim Read During a Dcache/Bcache MissIcache Fill from Memory Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Dcache Fill from MemoryBcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a ProbeDouble-Bit Fill Errors Double-Bit Fill ErrorsError Case Summary 3summarizes the various error cases and their ramificationsError Case Summary 10Error Detection and Error HandlingMchk Cstatdstreambcdbl Mchk CstatistreammemdblMchk Cstatdstreammemdbl Page 1lists the maximum electrical ratings for the 21264/EV67 Electrical CharacteristicsElectrical Data Maximum Electrical RatingsSignal Types DC CharacteristicsDC Characteristics IdcpowerInput Differential Amplifier Receiver IDA VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Clock Receiver IdaclkIOZ Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD Codtp11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver OppclkAC Characteristics AC CharacteristicsAC Test Conditions 13 AC Specifications TSU TDHTSU1 TDH2 AC Characteristics Page Operating Temperature at Heat Sink Center Tc Operating TemperatureAmbient temperature requirement Thermal ManagementOperating Temperature Θca at Various Airflows for 21264/EV6710-2Thermal Management Heat Sink Specifications Heat Sink SpecificationsType 1 Heat Sink 10-4Thermal ManagementType 2 Heat Sink Type 3 Heat Sink 10-6Thermal ManagementThermal Design Considerations Thermal Design ConsiderationsPage Dedicated Test Port Pins Testability and DiagnosticsTest Pins Testability and Diagnostics11-2Testability and Diagnostics SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port Srom Load OperationIeee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes 11-4Testability and Diagnostics TestStatH PinTestStatH Pin Built-in Self-Test Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Srom Initialization11-6Testability and Diagnostics Serial Instruction Cache Load OperationSee Appendix B for a listing of the Boundary-Scan Register Icache Bit Fields in an Srom LineReferences Page Table A-1 Instruction Format and Opcode Notation Alpha Instruction SetAlpha Instruction Summary Alpha Instruction Set A-1Alpha Instruction Summary Opr 11.24 Cmove if = zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.46 Cmove if ≥ zero15.0BC Convert quadword to Ffloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BE Convert quadword to Gfloating17.02C Fcmove if zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02B Fcmove if ≠ zeroOpr 1C.31 Pixel error Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Mem Load SfloatingMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Opr 10.02 Scaled add longword byReserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions Independent Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode SummaryIeee floating-point instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Floating-point operate instruction opcodesIeee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-15Cmpteq Cmptun Input Cmptlt Cmptle Input16Alpha Instruction Set Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn Alpha Instruction Set A-17Page 21264/EV67 Boundary-Scan Register Boundary-Scan RegisterBoundary-Scan Register Pllvdd21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-12PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9Restriction 9 PALmode Istream Address Ranges Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and GuidelinesRestriction 13 DTB Fill Flow Collision Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 14 HwretRestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Guideline 16 JSR-BAD VARestriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode 14PALcode Restrictions and GuidelinesGuideline 29 JSR, JMP, RET, and Jsrcor in PALcode Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-15 Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and GuidelinesRestriction 31 ICTLVA48 Update Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update PALcode Restrictions and Guidelines D-17Restriction 36 Updating Ictlsde Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 37 Updating VACTLVA48Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and GuidelinesRestriction 42 Updating VACTL, CCCTL, or CC IPRs Restriction 43 No Trappable Instructions Along withPALcode Restrictions and Guidelines D-21 Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and GuidelinesRestriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-2324PALcode Restrictions and Guidelines 21264/EV67-to-Bcache Pin Interconnections Forwarding Clock Pin GroupingsTable E-1 Bcache Forwarding Clock Pin Groupings Data Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Tag Pin UsageData and Tag Pin Usage Dual-Data Rate SSRAMsDual-Data Rate SSRAMs Table E-4 Dual-Data Rate Ssram Data Pin UsageTrstl Table E-5 Dual-Data Rate Ssram Tag Pin UsageGlossary BIU BSR Cisc CPU CmosCPI CSRDTB DMADram DTLFEU FepromFET FpgaGclk IDUITB IowbIpga JfetMBZ MAFMBO MipsNmos MSINaturally Aligned NvramPLA PALPGA PlccRAM PqfpProm RASRTL RiscROM SAMSIP SdramSimm SippUart StramTTL UnalignedVAF UnpredictableUvprom VDFWAR WriteblockIndex NumericsIndex-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12