Compaq specifications 21264/EV67-to-Bcache Pin Interconnections, Glossary Index

D.26	Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR	D–15
D.27	Restriction 31 : I_CTL[VA_48] Update	D–17
D.28	Restriction 32 : PCTR_CTL Update	D–17
D.29	Restriction 33 : HW_LD Physical/Lock Use	D–18
D.30	Restriction 34 : Writing Multiple ITB Entries in the Same PALcode Flow	D–18
D.31	Guideline 35 : HW_INT_CLR Update	D–18
D.32	Restriction 36 : Updating I_CTL[SDE]	D–18
D.33	Restriction 37 : Updating VA_CTL[VA_48]	D–18
D.34	Restriction 38 : Updating PCTR_CTL	D–18
D.35	Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow	D–19
D.36	Restriction 40: Scrubbing a Single-Bit Error	D–19
D.37	Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must Be in the Same Fetch Block	D–21
D.38	Restriction 42: Updating VA_CTL, CC_CTL, or CC IPRs	D–21
D.39	Restriction 43: No Trappable Instructions Along with HW_MTPR	D–21
D.40	Restriction 44: Not Applicable to the 21264/EV67	D–21
D.41	Restriction 45: No HW_JMP or JMP Instructions in PALcode	D–21
D.42	Restriction 46: Avoiding Live locks in Speculative Load CRD Handlers	D–22
D.43	Restriction 47: Cache Eviction for Single-Bit Cache Errors	D–22
D.44	Restriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity
	D–24

E 21264/EV67-to-Bcache Pin Interconnections

E.1	Forwarding Clock Pin Groupings	E–1
E.2	Late-WriteNon-Bursting SSRAMs	E–2
E.3	Dual-Data Rate SSRAMs	E–3

Glossary

Index

x Alpha 21264/EV67 Hardware Reference Manual