Compaq EV67, 21264 ProfileMe Mode Returned IPR Contents, 22Privileged Architecture Library Code

Performance Counter Support

For instructions that cause a trap, the last cycle in the window is the 2nd cycle after the trap. Mispredicted branches are included in this category.

For nontrapping instructions that retire, the last cycle in the window is the 2nd cycle after the instruction retires.

For instructions that abort, the last cycle in the window is the 2nd cycle after the trap that caused the abort.

For instructions that are squashed (such as TRAPB), the last cycle in the window is approximately the 2nd cycle after the squashed instruction would have aborted or retired.

Every non-squashed valid fetched instruction either aborts or retires, but not both. In either case, the instruction may also trap.

PCTR0 is disabled from counting until PCTR_CTL is next written.

5.Interrupt PALcode

When ISUM field PC[1:0] is set, execution of PCTR0’s or PCTR1’s interrupt PAL- code is performed.

6.Operating system interrupt handler

The handler should first read the IPRs in Table 6–13and then write PCTR_CTL to set up the next interrupt.

Table 6–13 ProfileMe Mode Returned IPR Contents

IPR Name	Relevant Fields	Meaning
PMPC[63:0]	All	Profiled PC.
I_STAT	ICM	Instruction was in a new Icache fill stream.
	TRP	Instruction caused a trap and was not in the shadow of
		a younger trapping instruction.
	MIS	Conditional branch mispredict.
	TRAP TYPE	Exception type code.
	LSO	Load-store order replay trap.
	OVR	Counter 0 overcount.
PCTR_CTL	VAL	Instruction retired valid.
	TAK	Branch direction if instruction is a conditional branch.
	PM_STALLED	Instruction stalled for at least one cycle between fetch
		and map stages of pipeline.
	PM_KILLED_BM	Instruction killed during or before cycle in which it
		was mapped.
	PCTR0[19:0]	Counter 0 value.
	PCTR1[19:0]	Counter 1 value.

6–22Privileged Architecture Library Code Alpha 21264/EV67 Hardware Reference Manual