Compaq 21264 Memory and I/O Address Space Instructions, Memory Address Space Load Instructions

Memory and I/O Address Space Instructions

The first instruction, CMOV1, tests the value of Ra and records the result of this test in a 65th bit of its destination register, newRc1. It also copies the value of the old physical destination register, oldRc, to newRc1.

The second instruction, CMOV2, then copies either the value in newRc1 or the value in Rb into a second physical destination register, newRc2, based on the CMOV predicate bit stored in newRc1.

In summary, the original CMOV instruction is decomposed into two dependent instruc- tions that each use a physical register from the free list.

To further simplify this operation, the two component instructions of a CMOV instruc- tion are driven through the mappers in successive cycles. Hence, if a fetch line contains n CMOV instructions, it takes n+1 cycles to run that fetch line through the mappers.

For example, the following fetch line:

ADD CMOVx SUB CMOVy

Results in the following three map cycles:

ADD CMOVx1

CMOVx2 SUB CMOVy1

CMOVy2

The Ebox executes integer CMOV instructions as two distinct 1-cycle latency opera- tions. The Fbox add pipeline executes floating-point CMOV instructions as two distinct 4-cycle latency operations.

2.8 Memory and I/O Address Space Instructions

This section provides an overview of the way the 21264/EV67 processes memory and I/ O address space instructions.

The 21264/EV67 supports, and internally recognizes, a 44-bit physical address space that is divided equally between memory address space and I/O address space. Memory address space resides in the lower half of the physical address space (PA[43]=0)

and I/O address space resides in the upper half of the physical address space (PA[43]=1).

The IQ can issue any combination of load and store instructions to the Mbox at the rate of two per cycle. The two lower Ebox subclusters, L0 and L1, generate the

48-bit effective virtual address for these instructions.

An instruction is defined to be newer than another instruction if it follows that instruc- tion in program order and is older if it precedes that instruction in program order.

2.8.1 Memory Address Space Load Instructions

The Mbox begins execution of a load instruction by translating its virtual address to a physical address using the DTB and by accessing the Dcache. The Dcache is virtually indexed, allowing these two operations to be done in parallel. The Mbox puts informa- tion about the load instruction, including its physical address, destination register, and data format, into the LQ.

Alpha 21264/EV67 Hardware Reference Manual Internal Architecture 2–27