Compaq EV67, 21264 specifications 40Internal Processor Registers, Setdirtyenable = Bcbankenable =

Cbox CSRs and IPRs

;SET_DIRTY_ENABLE = 6

;BC_BANK_ENABLE = 1

;BC_WRT_STS = 0

;

;The value for the write_many chain is based on Table 5–25.

;The value is sampled from MSB, 6 bits at a time, as it is written

;to EV6__DATA. Therefore, before the value can be shifted in, it must be

;inverted on a by 6 basis. The code then writes out 6 bits at a time,

;shifting right by 6 after each write.

;

;So the following transformation is done on the write_many value:

;[35:30][29:24][23:18][17:12][11:06][05:00] =>

;[05:00][11:06][17:12][23:18][29:24][35:30]

;

;WRITE_MANY chain = 0x07FBFFFFD

;value to be shifted in = 0xF7FFEFFC1

;Before the chain can be written, I_CTL[SBE] must be disabled,

;and the code must be forced into the Icache.

;

ALIGN_CACHE_BLOCK <^x47FF041F>; align with nops

mb		; wait for MEM-OP’s to complete
lda	r0, ^x0086(r31)	; load I_CTL
hw_mtpr	r0, EV6__I_CTL	; .....SDE=2, IC_EN=3, SBE=0
br	r0, .	; create dest address
addq	r0, #17, r0	; finish computing dest address
hw_mtpr r31, EV6__IC_FLUSH		; flush the Icache
bne	r31, .	; separate retires
hw_jmp_stall (r0)		; force flush
ALIGN_CACHE_BLOCK <^x47FF041F>		; align with nops
bc_config:
mb		; pull this block in Icache
lda	r1, ^xFFC1(r31)	; data[15:00] = 0xFFC1
ldah	r0, ^x7FFE(r31)	; data[31:16] = 0x7FFE
zap	r1, #^x0c, r1	; clear out bits [31:16]
bis	r1, r0, r1	; or in bits [31:16]
addq	r31, #6, r0	; shift in 6 x 6 bits
bc_config_shift_in:
hw_mtpr	r1, EV6__DATA	; shift in 6 bits
subq	r0, #1, r0	; decrement R0
beq	r0, bc_config_done	; done if R0 is zero
srl	r1, #6, r1	; align next 6 bits
br	r31, bc_config_shift_in	; continue shifting
bc_config_done:
hw_mtpr	r31, <EV6__MM_STAT ! 64>	; wait until last shift
beq	r31, bc_config_end	; predicts fall thru
br	r31, .-4	; predict infinite loop
bis	r31, r31, r31	; nop
bis	r31, r31, r31	; nop

bc_config_end:

5–40Internal Processor Registers Alpha 21264/EV67 Hardware Reference Manual