Compaq EV67, 21264 specifications ITB Fill, 16Privileged Architecture Library Code

Translation Buffer (TB) Fill Flows

•The conditional branch is placed in the code so that all of the MTPR instructions are issued and retired or none of them are issued and retired. This allows the TB fill hardware to update the TB whenever it sees the retiring of PTE1 and to ignore writes to TAG0/TAG1/PTE0/PTE1 in the interim between the issuing of those writes and a retire of PTE1.

•As an alternative to using I_CTL[TB_MB_EN] = 1 to enforce read ordering,

I_CTL[TB_MB_EN] can be set to 0 and the PALcode may use a bit in the PTE to indicate whether to do an explicit MB.

The flow example in 6-5 shows the code using pte_eco and the code not using pte_eco. It assumes the following:

–In a multi-processor configuration, if pte_eco is not enabled, it is necessary to enable tb_mb_en.

–In a uni-processor configuration, if pte_eco is not enabled, it is not necessary to enable tb_mb_en.

–At no time should pte_eco and tb_mb_en both be enabled.

•The value in DTB_PTEx[GH] determines whether the scoreboard mechanism alone is sufficient to guarantee all subsequent load/store instructions (implicit readers of the DTB) are ordered relative to the creation of a new DTB entry; whether all sub- sequent loads and stores to the loaded address will hit in the DTB.

–If DTB_PTE x[GH] is zero, the scoreboard mechanism alone is sufficient.

–If DTB_PTE x[GH] is not zero, the scoreboard mechanism alone is not suffi- cient (although this is not a problem). In this case, the new DTB entry is not visible to subsequent load/store instructions until after the MTPR DTB_PTE1 retires.

Issuing a HW_RET_STALL instead of a HW_RET would guarantee ordering, but is not necessary. Code executes correctly without the stall although execu- tion might result in two passes through the DTB miss flow, rather than one, because the re-execution of the memory operation after the first DTB miss might miss again.

This behavior is functionally correct because DTB loads that tag-match an existing DTB entry are ignored by the 21264/EV67 and the second DTB miss execution will load exactly the same entry as the first.

6.9.2 ITB Fill

Figure 6–6shows the ITB miss instructions flow.

Figure 6–6 ITB Miss Instructions Flow Example
hw_mfpr	r4,	EV6__IVA_FORM	; (0L) get vpte address
hw_mfpr	r23,	EV6__EXC_ADDR	; (0L) get exception address
lda	r6,	^x0FFF(r31)	; (xU) create mask for prot
bis	r31, r31, r31		; (xU) fill out fetch block
trap__itb_miss_vpte:
hw_ldq/v	r4,	(r4)	; (xL) get vpte
and	r4, r6, r5		; (xL) get prot bits
bltp_misc, trap__i1to1			; (xU) 1-to-1 => branch

6–16Privileged Architecture Library Code Alpha 21264/EV67 Hardware Reference Manual