Architecture, Addressing, Integer Data Types | Compaq EV67, 21264

The Architecture

direct access to low-level hardware functions. PALcode supports optimizations for mul- tiple operating systems, flexible memory-management implementations, and multi- instruction atomic sequences.

The Alpha architecture performs byte shifting and masking with normal 64-bit, regis- ter-to-register instructions. The 21264/EV67 performs single-byte and single-word load and store instructions.

1.1.1 Addressing

The basic addressable unit in the Alpha architecture is the 8-bit byte. The 21264/EV67 supports a 48-bit or 43-bit virtual address (selectable under IPR control).

Virtual addresses as seen by the program are translated into physical memory addresses by the memory-management mechanism. The 21264/EV67 supports a 44-bit physical address.

1.1.2 Integer Data Types

Alpha architecture supports the four integer data types listed in Table 1–1.

Table 1–1 Integer Data Types

Data Type	Description
Byte	A byte is 8 contiguous bits that start at an addressable byte boundary.
	A byte is an 8-bit value.
Word	A word is 2 contiguous bytes that start at an arbitrary byte boundary.
	A word is a 16-bit value.
Longword	A longword is 4 contiguous bytes that start at an arbitrary byte boundary. A
	longword is a 32-bit value.
Quadword	A quadword is 8 contiguous bytes that start at an arbitrary byte boundary.

Note:	Alpha implementations may impose a significant performance penalty
	when accessing operands that are not naturally aligned. Refer to the Alpha
	Architecture Handbook, Version 4 for details.

1.1.3 Floating-Point Data Types

The 21264/EV67 supports the following floating-point data types:

•Longword integer format in floating-point unit

•Quadword integer format in floating-point unit

•IEEE floating-point formats

–S_floating

–T_floating

•VAX floating-point formats

–F_floating

–G_floating

–D_floating (limited support)

1–2

Introduction

Alpha 21264/EV67 Hardware Reference Manual

Image 26

Compaq EV67, 21264 specifications Architecture, Addressing, Integer Data Types, Floating-Point Data Types

Contents

Hardware Reference Manual Revision/Update InformationAlpha 21264A Microprocessor DS-0028A-TE Alpha 21264/EV67 Hardware Reference Manual Table of Contents Hardware Interface Cache and External Interfaces Internal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr Mtfpcr Electrical Data Error Detection and Error HandlingTestability and Diagnostics Thermal Management Alpha Instruction Set 21264/EV67 Boundary-Scan Register 21264/EV67-to-Bcache Pin Interconnections Glossary Index Figures Xii Tables Xiv VDD Idcpower Page Audience ContentPreface Documentation Included by Reference Abbreviations Terminology and ConventionsFor example Addresses W1CW1S Aligned and Unaligned Do Not Care Signal NamesData Units External Undefined Do not care. a capital X represents any valid value Page Introduction IntroductionArchitecture Integer Data Types ArchitectureAddressing Floating-Point Data Types 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features Internal Architecture Internal Architecture21264/EV67 Microarchitecture Virtual Program Counter Logic Instruction Fetch, Issue, and Retire Unit21264/EV67 Microarchitecture 21264/EV67 Block Diagram Branch Predictor Local Predictor Global Predictor Choice Predictor Instruction-Stream Translation Buffer Register Rename Maps Integer Issue QueueInstruction Fetch Logic Floating-Point Issue Queue Hwret Retire Logic Integer Execution UnitException and Interrupt Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0 Floating-Point Execution Unit 10Internal Architecture 21264/EV67 contains two onchip primary-level caches External Cache and System Interface UnitOnchip Caches 12Internal Architecture Memory Reference UnitData Cache Srom Interface Pipeline OrganizationPipeline Organization Miss address file MAF Dstream translation buffer DTB 14Internal Architecture Stage 0 Instruction FetchStage 1 Instruction Slot Stage 3 Issue Stage 2 Map Pipeline Aborts Instruction Issue RulesInstruction Issue Rules Ebox and Fbox pipelines begin execution Instruction Issue Rules Instruction Group Definitions Instruction Name, Pipeline, and Types ITOFS, ITOFF, Itoft Ebox SlottingFTOIS, Ftoit Instruction Group Definitions and Pipeline Unit U U L E L U E E L L E U Hwmfpr Instruction Issue Rules Instruction LatenciesInstruction Class Latency in Cycles 20Internal Architecture Minimum Retire Latencies for Instruction Classes Instruction Retire RulesInstruction Retire Rules Floating-Point Divide/Square Root Early Retire Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 BSR/JSR Prefetch with Modify Intent LDS Instruction Load Instructions to R31 and F31Load Instructions to R31 and F31 Instructions Retired Without Execution Load Hit Speculation Special Cases of Alpha Instruction ExecutionPrefetch with the LDxL / STxC Instruction Sequence 24Internal Architecture Special Cases of Alpha Instruction Execution Pipeline Timing for Integer Load Instructions 26Internal Architecture Floating-Point Store InstructionsCmov Instruction Memory Address Space Load Instructions Memory and I/O Address Space InstructionsMemory and I/O Address Space Instructions 28Internal Architecture 2 I/O Address Space Load InstructionsRules for I/O Address Space Load Instruction Data Merging Rules for I/O Address Space Store Instruction Data Merging 4 I/O Address Space Store Instructions8shows some of the following rules MAF Memory Address Space Merging Rules MAF Memory Address Space Merging RulesInstruction Ordering MAF Merging Rules Mbox Order Traps Replay TrapsReplay Traps 10 Memory Reference Ordering Other Mbox Replay Traps 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Memory Barrier MB/WMB/TB Fill Flow MB Instruction Processing 12 TB Fill Flow Example Sequence WMB Instruction ProcessingTB Fill Flow 34Internal Architecture 13 TB Fill Flow Example Sequence Performance Measurement Support-Performance Counters Performance Measurement Support-Performance CountersFloating-Point Control Register Floating-point control register Fpcr is shown in Figure Floating-Point Control Register Amask Amask and Implver Instruction ValuesAmask and Implver Instruction Values Implver Design Examples Design Examples 13 Typical Multiprocessor Configuration 40Internal Architecture Hardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol Signal Pin Types Definitions 21264/EV67 Signal Names and Functions21264/EV67 Signal Names and Functions 21264/EV67 Signal Descriptions Dcokh Pllvdd 21264/EV67 Signal Descriptions by Function TestStatH SysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 10Hardware Interface Pllvdd AA5 Pin List Sorted by PGA Location 12Hardware Interface SysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware Interface Mechanical Specifications Mechanical Specifications 18Hardware Interface 21264/EV67 Packaging21264/EV67 Packaging 21264/EV67 Bottom View Pin Up Page Cache and External Interfaces Cache and External InterfacesIntroduction to the External Interfaces Introduction to the External Interfaces System Interface 21264/EV67 System and Bcache Interfaces Physical Address Considerations Commands and AddressesPhysical Address Considerations Second-Level Cache Bcache Interface ECB I/O MB/WMB Physical Address Considerations Bcache Structure Bcache Interface SignalsBcache Structure System Duplicate Tag Stores Victim Data Buffer Victim Data BufferCache Coherency Cache Coherency Basics 2lists the cache block states supported by the 21264/EV67 Cache CoherencyCache Block States 21264/EV67-Supported Cache Block States Cache Block State Transitions System Responses to 21264/EV67 CommandsCache Block State Transitions 10Cache and External Interfaces Cache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags 14Cache and External Interfaces Lock MechanismLock Mechanism Internal Eviction of LDxL Blocks Liveness and Fairness 16Cache and External Interfaces System PortSystem Port System Port Pins System Port Pins Program Values for Data-Sample/Drive CSRs System Port Programming the System Interface ClocksProgramming Values for System Interface Clocks 18Cache and External Interfaces Forwarded Clocks and Frame Clock Ratio 3 21264/EV67-to-System CommandsBank Interleave on Cache Block Boundary Mode 12 21264/EV67-to-System Command Fields Definitions Hit Mode11 Page Hit Mode of Operation 12describes the field definitions for Tables 4-10and 14 21264/EV67-to-System Commands Descriptions 4 21264/EV67-to-System Commands Descriptions14describes the 21264/EV67-to-system commands 13 Maximum Physical Address for Short Bus Format 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 17 21264/EV67 ProbeResponse Command ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 24Cache and External Interfaces 18 ProbeResponse Fields Descriptions SysAck and 21264/EV67-to-System Commands Flow Control18describes the ProbeResponse command fields 19 System-to-21264/EV67 Probe Commands System-to-21264/EV67 CommandsProbe Commands Four Cycles RVB RPB 22lists the next cache block state selected by Probe20 20 System-to-21264/EV67 Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 21 Data Movement Selection by Probe43 28Cache and External Interfaces Data Transfer Commands Two Cycles23 Data Transfer Command Format 24describes the SysDc40 field 24 SysDc40 Field Description 30Cache and External Interfaces Data Movement In and Out of the 21264/EV678.1 21264/EV67 Clock Basics Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External Interfaces Fast Data Disable Mode 26shows four example configurations and shows their use26 Cbox CSR SYSDCDELAY40 Examples SysDataInValidL 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL 34Cache and External Interfaces SysDataOutValidL SysFillValidL 36Cache and External Interfaces Data Wrapping28 Data Wrapping Rules 30 Wrap Interleave Order 30defines the interleaved scheme for the wrap order29 System Wrap and Deliver Data 31 Wrap Order for Double-Pumped Data Transfers Nonexistent Memory Processing31defines the wrap order for double-pumped data transfers 38Cache and External Interfaces 21264/EV67 Command NXM Address System/21264/EV67 Response 40Cache and External Interfaces 10.1 21264/EV67 Commands and System ProbesOrdering of System Port Transactions System Port Bcache Port Bcache Port 35 Range of Maximum Bcache Clock Ratios Bcache Port Pins36 Bcache Port Pins Bcache Clocking 44Cache and External Interfaces Setting the Period of the Cache Clock 37 BCCPUCLKDELAY10 Values38 BCCLKDELAY10 Values 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External Interfaces Bcache Data Read and Tag Read Transactions Bcache Transactions41 Data-Sample/Drive Cbox CSRs Bcache Data Write Transactions 48Cache and External Interfaces For example, in single-data mode When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio Dual-data mode, bcfrm is twice the ratio 50Cache and External Interfaces Relationship Between Read-to-Write Bcrdwrbubbles and rdwr Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd BcAddH234 44lists the combination of control pin assertion for BcDataInClkH and BcTagInClkH 46 Control Pin Assertion for Ramtype C47 Control Pin Assertion for Ramtype D Disabling the Bcache for Debugging InterruptsInterrupts Bcache Banking 54Cache and External Interfaces Internal Processor Registers Internal Processor Registers Mbox IPRs Cycle Counter Register CC Ebox IPRsEbox IPRs Cycle Counter Control Register Ccctl 2describes the Ccctl register fields Virtual Address Register VAVirtual Address Control Register Vactl Cycle Counter Control Register Fields Description Virtual Address Control Register Fields Description Virtual Address Format Register Vaform3describes the virtual address control register fields VAFORM32 ITB Tag Array Write Register Itbtag Ibox IPRsIbox IPRs ITB PTE Array Write Register Itbpte ITB Invalidate Single Register Itbis ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate All Register Itbia 4describes the ProfileMe PC register fields Ibox IPRs ProfileMe PC Register PmpcException Address Register Excaddr ProfileMe PC Fields Description Interrupt Enable and Current Processor Mode Register Iercm 13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals 10Internal Processor Registers Software Interrupt Request Register SirrIercm Register Fields Description Software Interrupt Request Register Fields Description Interrupt Summary Register Isum6describes the software interrupt request register fields Interrupt Summary Register Fields Description Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields 12Internal Processor Registers Hardware Interrupt Clear Register Fields Description Exception Summary Register Excsum8describes the hardware interrupt clear register fields Mchkd W1C 14Internal Processor Registers 9describes the exception summary register fieldsException Summary Register Fields Description 10describes the PAL base register fields PAL Base Register PalbaseIbox Control Register Ictl 10 PAL Base Register Fields Description 16Internal Processor Registers 11describes the Ibox control register fields11 Ibox Control Register Fields Description STWAIT64K SingleissuehMchken PCT1EN 18Internal Processor Registers Ibox Status Register IstatSpce MIS 12describes the Ibox status register fields12 Ibox Status Register Fields Description TRP 20Internal Processor Registers Icache Flush ASM Register Icflushasm Sleep Mode Register SleepIbox IPRs Icache Flush Register Icflush Clear Virtual-to-Physical Map Register Clrmap 22Internal Processor Registers 14describes the process context register fields14 Process Context Register Fields Description Ppce Performance Counter Control Register PctrctlFPE 24Internal Processor Registers 15describes the performance counter control register fields15 Performance Counter Control Register Fields Description DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 Mbox IPRsMbox IPRs 16 Performance Counter Control Register Input Select Fields DTB Alternate Processor Mode Register Dtbaltmode 26Internal Processor Registers Dstream TB Invalidate All Register Dtbia 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 18 Memory Management Status Register Fields Description Memory Management Status Register Mmstat18describes the memory management status register fields 28Internal Processor Registers ACV Mbox Control Register MctlFor 19describes the Mbox control register fields Erences to superpages result in access violationsDcache Control Register Dcctl 19 Mbox Control Register Fields Description 20 Dcache Control Register Fields Description Dcache Status Register Dcstat20describes the Dcache control register fields 21describes the Dcache status register fields Cbox CSRs and IPRsCbox CSRs and IPRs 21 Dcache Status Register Fields Description Cbox Writeonce Chain Description Cbox CSRs and IPRs Cbox Data Register CdataCbox Shift Register Cshft 22 describes the Cbox data register fields 24 Cbox Writeonce Chain Order 34Internal Processor Registers Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 Skewedfillmode 36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers 25describes the Cbox Writemany chain order from LSB to MSB 25 Cbox Writemany Chain Order Setdirtyenable = Bcbankenable = 40Internal Processor Registers Cbox CSRs and IPRs Cbox Read Register IPR Description 26 Cbox Read IPR Fields DescriptionPage Privileged Architecture Library Code Privileged Architecture Library CodePALcode Description PALmode Environment PALmode Environment Required PALcode Function Codes Required PALcode Function CodesOpcodes Reserved for PALcode Hwld Instruction 3describes the Hwld instruction fields Opcodes Reserved for PALcodeHwst Instruction Hwld Instruction Fields Descriptions Hwst Instruction Fields Descriptions Hwret Instruction4describes the Hwst instruction fields Hwret Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hint 6describes the Hwmfpr and Hwmtpr instructions fields Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms Hwmfpr and Hwmtpr Instructions Fields Descriptions Hardware Structure of Explicitly Written IPRs IPR Access Ordering Paired Instruction Fetch Order 10Privileged Architecture Library Code PALshadow Registers PALcode Emulation of the Fpcr PALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry Locations DTB Fill Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows 14Privileged Architecture Library Code Wr PTE LD-PTE, write TB Wr DataTb miss ITB Fill 16Privileged Architecture Library Code Performance Counter Support Performance Counter Support Aggregate Mode Precautions General PrecautionsAggregate Mode Programming Guidelines IPRs Used for Performance Counter Support Pctrctl SL0 10 Aggregate Mode Returned IPR ContentsOperation SL1 This input counts Mbox replay traps ProfileMe Mode Programming Guidelines11shows the counter modes that are used with Aggregate mode 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library Code ProfileMe Counting Mode Description Cycle counting Inum retire delay cycles 14 ProfileMe Mode Pctrctl Input Select Fields 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 24Privileged Architecture Library Code 21264/EV67 Reset State Machine Major Operations Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins Constraints Power Sequencing and Reset State for Signal Pins Signal Pin Reset State Clock Forwarding and System Clock Ratio Configuration Pllvdd Pin Signal Names and Initialization State PLL PLL Ramp Up BiST and Srom Load and the TestStatH Pin Clock Forward Reset and System Interface Initialization Power-Up Flow Signals and Their Constraints Effect on IPRs After Fault Reset Fault Reset FlowFault Reset Flow Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow Effect on IPRs After Transition Through Sleep Mode 10Initialization and Configuration Signals and Constraints for the Sleep Mode Sequence Warm Reset FlowWarm Reset Flow Effect on IPRs After Warm Reset Array Initialization Initialization Mode Processing12Initialization and Configuration Array Initialization Initialization Mode Processing EVICTENABLE0 14Initialization and Configuration Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State External Interface Initialization Internal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Ieee 1149.1 Test Port ResetReset State Machine 16Initialization and Configuration Reset State Machine 11 21264/EV67 Reset State Machine State Descriptions 18Initialization and Configuration Differential Reference Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description PLL Output Clocks Power-Up/Reset Clocking 20Initialization and Configuration Error Detection and Error Handling Error Detection and Error Handling21264/EV67 Error Detection Mechanisms Dcache Tag Parity Error Data Error Correction CodeIcache Data or Tag Parity Error Data Error Correction Code Load Instruction Dcache Data Single-Bit Correctable ECC ErrorDcache Data Single-Bit Correctable ECC Error Dcache Store Second Error Dcache Store Second ErrorDcache Duplicate Tag Parity Error Store Instruction Quadword or Smaller Bcache Tag Parity Error Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Icache Fill from Bcache Bcache Victim Read Bcache Victim Read During a Dcache/Bcache Miss Icache Fill from Memory Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Dcache Fill from Memory Bcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a Probe Double-Bit Fill Errors Double-Bit Fill ErrorsError Case Summary 3summarizes the various error cases and their ramifications Error Case Summary 10Error Detection and Error Handling Mchk Cstatdstreammemdbl Mchk CstatdstreambcdblMchk Cstatistreammemdbl Page 1lists the maximum electrical ratings for the 21264/EV67 Electrical CharacteristicsElectrical Data Maximum Electrical Ratings Signal Types DC CharacteristicsDC Characteristics Idcpower Input Differential Amplifier Receiver IDA VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Clock Receiver Idaclk IOZ Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD Codtp 11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver Oppclk AC Test Conditions AC CharacteristicsAC Characteristics 13 AC Specifications TSU TDH TSU1 TDH2 AC Characteristics Page Operating Temperature at Heat Sink Center Tc Operating TemperatureAmbient temperature requirement Thermal Management 10-2Thermal Management Operating TemperatureΘca at Various Airflows for 21264/EV67 Heat Sink Specifications Heat Sink Specifications Type 1 Heat Sink 10-4Thermal Management Type 2 Heat Sink Type 3 Heat Sink 10-6Thermal Management Thermal Design Considerations Thermal Design ConsiderationsPage Dedicated Test Port Pins Testability and DiagnosticsTest Pins Testability and Diagnostics 11-2Testability and Diagnostics SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port Srom Load Operation Ieee 1149.1 Instructions and Opcodes Ieee 1149.1 PortIeee 1149.1 Port TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Built-in Self-Test Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Srom Initialization 11-6Testability and Diagnostics Serial Instruction Cache Load Operation References See Appendix B for a listing of the Boundary-Scan RegisterIcache Bit Fields in an Srom Line Page Table A-1 Instruction Format and Opcode Notation Alpha Instruction SetAlpha Instruction Summary Alpha Instruction Set A-1 Alpha Instruction Summary Opr 11.24 Cmove if = zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.46 Cmove if ≥ zero 15.0BC Convert quadword to Ffloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BE Convert quadword to Gfloating 17.02C Fcmove if zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02B Fcmove if ≠ zero Opr 1C.31 Pixel error Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Mem Load Sfloating Mfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Opr 10.02 Scaled add longword by Opcodes Reserved for Compaq Reserved OpcodesReserved Opcodes Ieee Floating-Point Instructions Ieee Floating-Point Instructions VAX Floating-Point Instructions VAX Floating-Point InstructionsIndependent Floating-Point Instructions Opcode Summary Opcode Summary Ieee floating-point instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Floating-point operate instruction opcodes 14Alpha Instruction Set Ieee Floating-Point ConformanceIeee Floating-Point Conformance Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-15 16Alpha Instruction Set Cmpteq Cmptun InputCmptlt Cmptle Input Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn Alpha Instruction Set A-17Page 21264/EV67 Boundary-Scan Register Boundary-Scan Register Boundary-Scan Register Pllvdd 21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-1 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9 Restriction 9 PALmode Istream Address Ranges Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and Guidelines Restriction 13 DTB Fill Flow Collision Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 14 Hwret Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Guideline 16 JSR-BAD VA PALcode Restrictions and Guidelines D-13 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode 14PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-15 Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodeRestriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 31 ICTLVA48 Update Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update PALcode Restrictions and Guidelines D-17 Restriction 36 Updating Ictlsde Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 37 Updating VACTLVA48 Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-21 Restriction 42 Updating VACTL, CCCTL, or CC IPRsRestriction 43 No Trappable Instructions Along with Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 24PALcode Restrictions and Guidelines Table E-1 Bcache Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsForwarding Clock Pin Groupings Data Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Tag Pin Usage Data and Tag Pin Usage Dual-Data Rate SSRAMsDual-Data Rate SSRAMs Table E-4 Dual-Data Rate Ssram Data Pin Usage Trstl Table E-5 Dual-Data Rate Ssram Tag Pin Usage Glossary BIU BSR Cisc CPU CmosCPI CSR DTB DMADram DTL FEU FepromFET Fpga Gclk IDU ITB IowbIpga Jfet MBZ MAFMBO Mips Nmos MSINaturally Aligned Nvram PLA PALPGA Plcc RAM PqfpProm RAS RTL RiscROM SAM SIP SdramSimm Sipp Uart StramTTL Unaligned VAF UnpredictableUvprom VDF WAR Writeblock Index Numerics Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12