Compaq 21264 26shows four example configurations and shows their use, Fast Data Disable Mode

System Port

Table 4–26shows four example configurations and shows their use of the

SYSDC_DELAY[4:0].

Table 4–26 Cbox CSR SYSDC_DELAY[4:0] Examples

System	Bit Rate	System Framing Clock Ratio1	SYSDC_DELAY
System 1	1.5X	4:1	5	(3 SYSCLK cycles)
System 2	2.0X	2:1	2	(3 SYSCLK cycles)
System 3	2.5X	2:1	0	(2 SYSCLK cycles)
System 4	4X	2:1	6	(2 SYSCLK cycles)

1The system framing clock ratio is the number of INT_FWD_CLK cycles per SYSCLK cycles.

System 1 has six GCLKs to every SYSCLK and only sends 4-cycle commands to the 21264/EV67. Thus, a period of three SYSCLKs between the SysDc command and data leaves a period of 15 GCLKs between SysDc and data (SysDc is in the middle of the 4- cycle command). A SYSDC_DELAY[4:0] of five would align sampling and receipt of SysData.

System 2 has four GCLKs in every SYSCLK, so leading data by three SYSCLK cycles, and programming the SYSDC_DELAY[4:0] to two, aligns sampling and receiving.

Timing for systems 3 and 4 is derived in a similar manner.

Note: The maximum valid value for SYSDC_DELAY must be less than the min- imum number of GCLK cycles between two consecutive SYSDC com- mands to the 21264/EV67.

If a fast data transfer is interrupted and fails to complete, the system must use the con- ventional protocol to send a SysDc WriteData command to the 21264/EV67, removing the desired data buffer. Section 4.7.8.3 describes the timing events for transferring data from the 21264/EV67 to the system.

4.7.8.3 Fast Data Disable Mode

The system controls all data movement to and from the 21264/EV67. Movement of data into and out of the 21264/EV67 is preceded by a SysDc command. The 21264/EV67 drivers are only enabled for the duration of an 8-cycle transfer of data from the 21264/ EV67 to the system. Systems must ensure that there is no overlap of enabled drivers and that there is adequate settle time on the SysData bus.

Given a SysDc fill command, the 21264/EV67 samples data 10 + SYSDC_DELAY GCLK cycles after the command is perceived within the 21264/EV67 clock domain. Because there is no linkage with the output driver, fills into the 21264/EV67 are not affected by the SYS_RCV_MUX_PRESET[1:0] value.

In both modes, given a SysDc write command, the 21264/EV67 looks for the next SYSCLK edge 8.5 cycles after perceiving the SysDc write command in its clock domain. Because the SysDc write command must be perceived before its use, SysDc write commands are dependent upon the amount of delay introduced by Cbox CSR SYS_RCV_MUX_CNT_PRESET[1:0].

Alpha 21264/EV67 Hardware Reference Manual Cache and External Interfaces 4–33