Compaq 21264, EV67 Mchken, STWAIT64K, PCT1EN, PCT0EN, Singleissueh, Slrcv, Slxmit, Hwe

Ibox IPRs

Table 5–11 Ibox Control Register Fields Description (Continued)

Name	Extent	Type	Description
MCHK_EN	[21]	RW,0	Machine check enable — set to enable machine checks.
ST_WAIT_64K	[20]	RW,0	The stWait table is used to reduce load/store order traps.
			When set, the stWait table is cleared after 64K cycles. When
			clear, the stWait table is cleared after 16K cycles. See Sec-
			tion 2.11.
PCT1_EN	[19]	RW,0	Enable performance counter #1. If this bit is one, the perfor-
			mance counter will count if either the system (SPCE) or pro-
			cess (PPCE) performance counter enable is asserted.
PCT0_EN	[18]	RW,0	Enable performance counter #0. If this bit is one, the perfor-
			mance counter will count if EITHER the system (SPCE) or
			process (PPCE) performance counter enable is set.
SINGLE_ISSUE_H	[17]	RW,0	When set, this bit forces instructions to issue only from the
			bottom-most entries of the IQ and FQ.
VA_FORM_32	[16]	RW,0	This bit controls address formatting on a read of the
			IVA_FORM register.
VA_48	[15]	RW,0	This bit controls the format applied to effective virtual
			addresses by the IVA_FORM register and the Ibox virtual
			address sign extension checkers. When VA_48 is clear, 43-
			bit virtual address format is used, and when VA_48 is set,
			48-bit virtual address format is used. The effect of this bit on
			the IVA_FORM register is identical to the effect of
			VA_CTL[VA_48] on the VA_FORM register. See Section
			5.1.5.
			When VA_48 is set, the sign extension checkers generate an
			ACV if va[63:0] ≠ SEXT(va[47:0]). When VA_48 is clear,
			the sign extension checkers generate an ACV if va[63:0] ≠
			SEXT(va[42:0]).
			This bit also affects DTB_DOUBLE traps. If set, the DTB
			double miss traps vector to the DTB_DOUBLE_4 entry
			point.
			DTB_DOUBLE PALcode flow selection is not affected by
			VA_CTL[VA_48].
SL_RCV	[14]	RO	See Section 11.2.
SL_XMIT	[13]	WO	When set, drives a value on SromClk_H. See Section 11.2.
HWE	[12]	RW,0	If set, allow PALRES intructions to be executed in kernel
			mode. Note that modification of the ITB while in kernel
			mode/native mode may cause UNPREDICTABLE behavior.
BP_MODE[1:0]	[11:10]	RW,0	Branch Prediction Mode Selection.
			BP_MODE[1], if set, forces all branches to be predicted to

fall through. If clear, the dynamic branch predictor is chosen. BP_MODE[0]. If set, the dynamic branch predictor chooses local history prediction. If clear, the dynamic branch predic- tor chooses local or global prediction based on the state of the chooser.

Alpha 21264/EV67 Hardware Reference Manual Internal Processor Registers 5–17