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Compaq 21264, EV67 See Appendix B for a listing of the Boundary-Scan Register, References

Models: 21264 EV67

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Notes on IEEE 1149.1 Operation and Compliance

The instruction cache lines are loaded in the reverse order. If the fetch_count(9,0) is zero, then, no instruction cache lines are loaded. Since the valid bits are already cleared by the BiST operation, the first instruction fetch is missed in the instruction cache and the chip seeks instructions from the offchip memory.

Table 11–3 Icache Bit Fields in an SROM Line

Fetch Bit	Icache Data	Fetch Bit	Icache Data	Fetch Bit	Icache Data
0	par-MBZ	86	par-MBZ	172	lp_train
1	c[3]	87	c[0]	173:175	lp_src(2:0)
2:27	i[3](25,20,24,19,23,18,22,17	88:113	i[0](25,20,24,19,3,18,22,17,	176:181	lp_idx(14:9)
	,21,16:0)		21,16:0)
28	c[2]	114	c[1]	182:186	lp_idx(8:4)
29:42	i[2](25,20,24,19,	115:128	i[1] (25,20,24,19,	187	lp_idx(15)
	23,18,22,17,21,16:12)		23,18,22,17,21,16:12)
43	parity	129	parity	188:192	lp_ssp[4:0]
44:55	i[2](11:0)	130:141	i[1](11:0)	—	—
56	dv[3]	142	dv[0]	—	—
57:59	iq[3](2:0)	143:145	iq[0](2:0)	—	—
60:65	i[3](26:31)	146:151	i[0](26:31)	—	—
66,68	ea[3](2:0)	152:154	ea[0](2:0)	—	—
69	dv[2]	155	dv[1]	—	—
70,72	iq[2](2:0)	156:158	iq[1](2:0)	—	—
73:78	i[2](26:31)	159:164	i[1](26:31)	—	—
79:81	ea[2](2:0)	165:167	ea[1](2:0)	—	—
82:85	tr(7:4)	168:171	tr(0:3)	—	—

Refer to the Alpha Motherboards Software Developer’s Kit (SDK) for example C code that calculates the predecode values of a serial Icache load.

11.6Notes on IEEE 1149.1 Operation and Compliance

1.IEEE 1149.1 port pins on the 21264/EV67 are not pulled up or pulled down on the chip. The necessary pull-up or pull-down function must be implemented on the board.

2.Tms_H should not change when Trst_L is being deasserted.

References

IEEE Std. 1149.1-1993A Test Access Port and Boundary Scan Architecture.

See Appendix B for a listing of the Boundary-Scan Register.

Alpha 21264/EV67 Hardware Reference Manual

Testability and Diagnostics 11–7

Image 265

Compaq 21264 See Appendix B for a listing of the Boundary-Scan Register, Icache Bit Fields in an Srom Line, References

Contents

Alpha 21264A Microprocessor Revision/Update InformationHardware Reference Manual DS-0028A-TEAlpha 21264/EV67 Hardware Reference Manual Table of Contents Cache and External Interfaces Hardware InterfaceInternal Processor Registers Privileged Architecture Library Code Mffpcr Mtfpcr Initialization and ConfigurationTestability and Diagnostics Error Detection and Error HandlingElectrical Data Thermal Management21264/EV67 Boundary-Scan Register Alpha Instruction SetGlossary Index 21264/EV67-to-Bcache Pin InterconnectionsFigures Xii Tables Xiv VDD Idcpower Page Preface ContentAudience Documentation Included by Reference For example Terminology and ConventionsAbbreviations W1S W1CAddresses Aligned and UnalignedData Units Signal NamesDo Not Care ExternalUndefined Do not care. a capital X represents any valid value Page Architecture IntroductionIntroduction Addressing ArchitectureInteger Data Types Floating-Point Data Types21264/EV67 Microprocessor Features 21264/EV67 Microprocessor Features21264/EV67 Microprocessor Features 21264/EV67 Microarchitecture Internal ArchitectureInternal Architecture 21264/EV67 Microarchitecture Instruction Fetch, Issue, and Retire UnitVirtual Program Counter Logic Branch Predictor 21264/EV67 Block DiagramGlobal Predictor Local PredictorInstruction-Stream Translation Buffer Choice PredictorInstruction Fetch Logic Integer Issue QueueRegister Rename Maps Hwret Floating-Point Issue QueueException and Interrupt Logic Integer Execution UnitRetire Logic Integer Execution Unit-Clusters 0 PERR, MINxxx, MAXxxx, UNPKxx, PKxx10Internal Architecture Floating-Point Execution UnitOnchip Caches External Cache and System Interface Unit21264/EV67 contains two onchip primary-level caches Data Cache Memory Reference Unit12Internal Architecture Pipeline Organization Pipeline OrganizationSrom Interface Miss address file MAF Dstream translation buffer DTBStage 1 Instruction Slot Stage 0 Instruction Fetch14Internal Architecture Stage 2 Map Stage 3 IssueInstruction Issue Rules Instruction Issue RulesPipeline Aborts Ebox and Fbox pipelines begin executionInstruction Name, Pipeline, and Types Instruction Issue Rules Instruction Group DefinitionsFTOIS, Ftoit Ebox SlottingITOFS, ITOFF, Itoft Instruction Group Definitions and Pipeline UnitU U L E L U E E L L E U Instruction Class Latency in Cycles Instruction Issue Rules Instruction LatenciesHwmfpr 20Internal ArchitectureInstruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Retire of Operate Instructions into R31/F31 Retire of Operate Instructions into R31/F31Floating-Point Divide/Square Root Early Retire BSR/JSRLoad Instructions to R31 and F31 Load Instructions to R31 and F31Prefetch with Modify Intent LDS Instruction Instructions Retired Without ExecutionPrefetch with the LDxL / STxC Instruction Sequence Special Cases of Alpha Instruction ExecutionLoad Hit Speculation 24Internal ArchitecturePipeline Timing for Integer Load Instructions Special Cases of Alpha Instruction ExecutionCmov Instruction Floating-Point Store Instructions26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging 2 I/O Address Space Load Instructions28Internal Architecture 8shows some of the following rules 4 I/O Address Space Store InstructionsRules for I/O Address Space Store Instruction Data Merging Instruction Ordering MAF Memory Address Space Merging RulesMAF Memory Address Space Merging Rules MAF Merging RulesReplay Traps Replay TrapsMbox Order Traps 10 Memory Reference OrderingWrite Buffer and the WMB Instruction 12 I/O Write Buffer and the WMB InstructionOther Mbox Replay Traps Memory Barrier MB/WMB/TB Fill FlowMB Instruction Processing TB Fill Flow WMB Instruction Processing12 TB Fill Flow Example Sequence 34Internal Architecture13 TB Fill Flow Example Sequence Floating-Point Control Register Performance Measurement Support-Performance CountersPerformance Measurement Support-Performance Counters Floating-point control register Fpcr is shown in FigureFloating-Point Control Register Amask and Implver Instruction Values Amask and Implver Instruction ValuesAmask ImplverDesign Examples Design Examples40Internal Architecture 13 Typical Multiprocessor ConfigurationHardware Interface 21264/EV67 Microprocessor Logic SymbolHardware Interface 21264/EV67 Microprocessor Logic Symbol 21264/EV67 Microprocessor Logic Symbol21264/EV67 Signal Names and Functions 21264/EV67 Signal Names and FunctionsSignal Pin Types Definitions 21264/EV67 Signal DescriptionsDcokh Pllvdd TestStatH 21264/EV67 Signal Descriptions by FunctionSysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 Pllvdd 10Hardware InterfaceAA5 12Hardware Interface Pin List Sorted by PGA LocationSysDataL28 14Hardware Interface BcDataH70 SysDataL5 16Hardware Interface Ground and Power VSS and VDD Pin ListMechanical Specifications Mechanical Specifications21264/EV67 Packaging 21264/EV67 Packaging18Hardware Interface 21264/EV67 Bottom View Pin Up Page Introduction to the External Interfaces Cache and External InterfacesCache and External Interfaces Introduction to the External Interfaces 21264/EV67 System and Bcache Interfaces System InterfacePhysical Address Considerations Commands and AddressesPhysical Address Considerations Second-Level Cache Bcache InterfaceMB/WMB ECB I/OPhysical Address Considerations Bcache Structure Bcache Interface SignalsBcache Structure System Duplicate Tag StoresCache Coherency Victim Data BufferVictim Data Buffer Cache Coherency BasicsCache Block States Cache Coherency2lists the cache block states supported by the 21264/EV67 21264/EV67-Supported Cache Block StatesCache Block State Transitions System Responses to 21264/EV67 CommandsCache Block State Transitions 10Cache and External InterfacesCache Coherency Using SysDc Commands 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Liveness and Fairness Internal Eviction of LDxL BlocksSystem Port System Port16Cache and External Interfaces System Port Pins System Port PinsProgramming Values for System Interface Clocks System Port Programming the System Interface ClocksProgram Values for Data-Sample/Drive CSRs 18Cache and External InterfacesBank Interleave on Cache Block Boundary Mode 3 21264/EV67-to-System CommandsForwarded Clocks and Frame Clock Ratio 11 Page Hit Mode of Operation Hit Mode12 21264/EV67-to-System Command Fields Definitions 12describes the field definitions for Tables 4-10and14describes the 21264/EV67-to-system commands 4 21264/EV67-to-System Commands Descriptions14 21264/EV67-to-System Commands Descriptions 13 Maximum Physical Address for Short Bus Format22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 16 Programming SETDIRTYENABLE20 ProbeResponse Commands Command40 =17 21264/EV67 ProbeResponse Command 24Cache and External Interfaces18describes the ProbeResponse command fields SysAck and 21264/EV67-to-System Commands Flow Control18 ProbeResponse Fields Descriptions Probe Commands Four Cycles System-to-21264/EV67 Commands19 System-to-21264/EV67 Probe Commands RVB RPB21 lists the data movement selected by Probe43 20 System-to-21264/EV67 Probe Commands Fields Descriptions22lists the next cache block state selected by Probe20 21 Data Movement Selection by Probe4323 Data Transfer Command Format Data Transfer Commands Two Cycles28Cache and External Interfaces 24 SysDc40 Field Description 24describes the SysDc40 field8.1 21264/EV67 Clock Basics Data Movement In and Out of the 21264/EV6730Cache and External Interfaces Fast Data Mode 32Cache and External Interfaces 25 Sysclk Cycles Between SysAddOut and SysData26 Cbox CSR SYSDCDELAY40 Examples 26shows four example configurations and shows their useFast Data Disable Mode SysDataInValidL and SysDataOutValidL 27 Four Timing ExamplesSysDataInValidL 34Cache and External InterfacesSysFillValidL SysDataOutValidL28 Data Wrapping Rules Data Wrapping36Cache and External Interfaces 29 System Wrap and Deliver Data 30defines the interleaved scheme for the wrap order30 Wrap Interleave Order 31defines the wrap order for double-pumped data transfers Nonexistent Memory Processing31 Wrap Order for Double-Pumped Data Transfers 38Cache and External Interfaces21264/EV67 Command NXM Address System/21264/EV67 Response Ordering of System Port Transactions 10.1 21264/EV67 Commands and System Probes40Cache and External Interfaces System Port Bcache Port Bcache Port36 Bcache Port Pins Bcache Port Pins35 Range of Maximum Bcache Clock Ratios 44Cache and External Interfaces Bcache Clocking38 BCCLKDELAY10 Values 37 BCCPUCLKDELAY10 ValuesSetting the Period of the Cache Clock 46Cache and External Interfaces 39 Program Values to Set the Cache Clock Period Single-Data41 Data-Sample/Drive Cbox CSRs Bcache TransactionsBcache Data Read and Tag Read Transactions 48Cache and External Interfaces Bcache Data Write TransactionsWhen the ratio is odd, bcfrm is twice the ratio When the ratio is even, bcfrm is equal to the ratioFor example, in single-data mode Dual-data mode, bcfrm is twice the ratio50Cache and External Interfaces Relationship Between Write-to-Read Bcwrrdbubbles and wrrd Pin DescriptionsRelationship Between Read-to-Write Bcrdwrbubbles and rdwr BcAddH23444lists the combination of control pin assertion for 47 Control Pin Assertion for Ramtype D 46 Control Pin Assertion for Ramtype CBcDataInClkH and BcTagInClkH Interrupts Bcache Banking InterruptsDisabling the Bcache for Debugging 54Cache and External InterfacesInternal Processor Registers Internal Processor RegistersMbox IPRs Ebox IPRs Ebox IPRsCycle Counter Register CC Cycle Counter Control Register CcctlVirtual Address Control Register Vactl Virtual Address Register VA2describes the Ccctl register fields Cycle Counter Control Register Fields Description3describes the virtual address control register fields Virtual Address Format Register VaformVirtual Address Control Register Fields Description VAFORM32Ibox IPRs Ibox IPRsITB Tag Array Write Register Itbtag ITB PTE Array Write Register ItbpteITB Invalidate All Register Itbia ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate Single Register Itbis Exception Address Register Excaddr Ibox IPRs ProfileMe PC Register Pmpc4describes the ProfileMe PC register fields ProfileMe PC Fields Description13shows Ivaform when ICTLVA48 equals 0 ICTLVAFORM32 equals Interrupt Enable and Current Processor Mode Register IercmIercm Register Fields Description Software Interrupt Request Register Sirr10Internal Processor Registers 6describes the software interrupt request register fields Interrupt Summary Register IsumSoftware Interrupt Request Register Fields Description 7describes the interrupt summary register fields Hardware Interrupt Clear Register HwintclrInterrupt Summary Register Fields Description 12Internal Processor Registers8describes the hardware interrupt clear register fields Exception Summary Register ExcsumHardware Interrupt Clear Register Fields Description Mchkd W1CException Summary Register Fields Description 9describes the exception summary register fields14Internal Processor Registers Ibox Control Register Ictl PAL Base Register Palbase10describes the PAL base register fields 10 PAL Base Register Fields Description11 Ibox Control Register Fields Description 11describes the Ibox control register fields16Internal Processor Registers Mchken SingleissuehSTWAIT64K PCT1ENSpce Ibox Status Register Istat18Internal Processor Registers 12 Ibox Status Register Fields Description 12describes the Ibox status register fieldsMIS TRP20Internal Processor Registers Ibox IPRs Icache Flush Register Icflush Sleep Mode Register SleepIcache Flush ASM Register Icflushasm Clear Virtual-to-Physical Map Register Clrmap14 Process Context Register Fields Description 14describes the process context register fields22Internal Processor Registers FPE Performance Counter Control Register PctrctlPpce 15 Performance Counter Control Register Fields Description 15describes the performance counter control register fields24Internal Processor Registers Mbox IPRs Mbox IPRsDTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 16 Performance Counter Control Register Input Select Fields26Internal Processor Registers DTB Alternate Processor Mode Register DtbaltmodeDstream TB Invalidate All Process ASM=0 Register Dtbiap 17 DTB Alternate Processor Mode Register Fields DescriptionDstream TB Invalidate All Register Dtbia Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,118describes the memory management status register fields Memory Management Status Register Mmstat18 Memory Management Status Register Fields Description 28Internal Processor RegistersFor Mbox Control Register MctlACV Dcache Control Register Dcctl Erences to superpages result in access violations19describes the Mbox control register fields 19 Mbox Control Register Fields Description20describes the Dcache control register fields Dcache Status Register Dcstat20 Dcache Control Register Fields Description Cbox CSRs and IPRs Cbox CSRs and IPRs21describes the Dcache status register fields 21 Dcache Status Register Fields DescriptionCbox Shift Register Cshft Cbox CSRs and IPRs Cbox Data Register CdataCbox Writeonce Chain Description 22 describes the Cbox data register fields34Internal Processor Registers 24 Cbox Writeonce Chain OrderSkewedfillmode Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN02336Internal Processor Registers SYSCLKDELAY10 38Internal Processor Registers Cbox Writemany Chain Description25 Cbox Writemany Chain Order 25describes the Cbox Writemany chain order from LSB to MSB40Internal Processor Registers Setdirtyenable = Bcbankenable =26 Cbox Read IPR Fields Description Cbox CSRs and IPRs Cbox Read Register IPR DescriptionPage PALcode Description Privileged Architecture Library CodePrivileged Architecture Library Code PALmode Environment PALmode EnvironmentOpcodes Reserved for PALcode Required PALcode Function CodesRequired PALcode Function Codes Hwld InstructionHwst Instruction Opcodes Reserved for PALcode3describes the Hwld instruction fields Hwld Instruction Fields Descriptions4describes the Hwst instruction fields Hwret InstructionHwst Instruction Fields Descriptions 5describes the Hwret instruction fields Hwmfpr and Hwmtpr InstructionsHwret Instruction Fields Descriptions HintInternal Processor Register Access Mechanisms Internal Processor Register Access Mechanisms6describes the Hwmfpr and Hwmtpr instructions fields Hwmfpr and Hwmtpr Instructions Fields DescriptionsHardware Structure of Explicitly Written IPRs Paired Instruction Fetch Order IPR Access Ordering10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow RegistersPALcode Entry Points PALcode Exception Entry Locations PALcode Exception Entry PointsTranslation Buffer TB Fill Flows Translation Buffer TB Fill FlowsDTB Fill 14Privileged Architecture Library CodeTb miss Wr DataWr PTE LD-PTE, write TB 16Privileged Architecture Library Code ITB FillPerformance Counter Support Performance Counter SupportAggregate Mode Programming Guidelines General PrecautionsAggregate Mode Precautions IPRs Used for Performance Counter SupportOperation 10 Aggregate Mode Returned IPR ContentsPctrctl SL0 SL111shows the counter modes that are used with Aggregate mode ProfileMe Mode Programming GuidelinesThis input counts Mbox replay traps 12 Cmov Decomposed 22Privileged Architecture Library Code 13 ProfileMe Mode Returned IPR ContentsInum retire delay cycles ProfileMe Counting Mode Description Cycle countingCounter Modes for ProfileMe Mode 14shows the counter modes that are used with ProfileMe mode14 ProfileMe Mode Pctrctl Input Select Fields 24Privileged Architecture Library CodePower-Up Reset Flow and the ResetL and Dcokh Pins Initialization and Configuration21264/EV67 Reset State Machine Major Operations Initialization and ConfigurationConstraints Power-Up Reset Flow and the ResetL and Dcokh PinsSignal Pin Reset State Power Sequencing and Reset State for Signal PinsPllvdd Clock Forwarding and System Clock Ratio ConfigurationPLL Pin Signal Names and Initialization StateBiST and Srom Load and the TestStatH Pin PLL Ramp UpPower-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface InitializationFault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow10Initialization and Configuration Effect on IPRs After Transition Through Sleep ModeWarm Reset Flow Warm Reset FlowSignals and Constraints for the Sleep Mode Sequence Effect on IPRs After Warm Reset12Initialization and Configuration Initialization Mode ProcessingArray Initialization Array InitializationEVICTENABLE0 Initialization Mode Processing10 Internal Processor Registers at Power-Up Reset State Internal Processor Register Power-Up Reset State14Initialization and Configuration External Interface InitializationInternal Processor Register Power-Up Reset State Reset State Machine Ieee 1149.1 Test Port ResetIeee 1149.1 Test Port Reset 16Initialization and Configuration11 21264/EV67 Reset State Machine State Descriptions Reset State Machine18Initialization and Configuration Phase-Lock Loop PLL Functional Description Phase-Lock Loop PLL Functional DescriptionDifferential Reference Clocks PLL Output Clocks20Initialization and Configuration Power-Up/Reset Clocking21264/EV67 Error Detection Mechanisms Error Detection and Error HandlingError Detection and Error Handling Icache Data or Tag Parity Error Data Error Correction CodeDcache Tag Parity Error Data Error Correction CodeDcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Duplicate Tag Parity Error Dcache Store Second ErrorDcache Store Second Error Store Instruction Quadword or SmallerBcache Data Single-Bit Correctable ECC Error Bcache Tag Parity ErrorBcache Tag Parity Error Icache Fill from BcacheBcache Victim Read During a Dcache/Bcache Miss Bcache Victim ReadMemory/System Port Single-Bit Data Correctable ECC Error Memory/System Port Single-Bit Data Correctable ECC ErrorIcache Fill from Memory Dcache Fill from MemoryBcache Data Single-Bit Correctable ECC Error on a Probe Bcache Data Single-Bit Correctable ECC Error on a ProbeError Case Summary Double-Bit Fill ErrorsDouble-Bit Fill Errors 3summarizes the various error cases and their ramifications10Error Detection and Error Handling Error Case SummaryMchk Cstatistreammemdbl Mchk CstatdstreambcdblMchk Cstatdstreammemdbl Page Electrical Data Electrical Characteristics1lists the maximum electrical ratings for the 21264/EV67 Maximum Electrical RatingsDC Characteristics DC CharacteristicsSignal Types IdcpowerInput DC Reference Pin Idcref VDD IdcpowerInput Differential Amplifier Receiver IDA Input Differential Amplifier Clock Receiver IdaclkPin Type Open-Drain Output Driver OOD Pin Type Open-Drain Driver for Test Pins OodtpIOZ Codtp12 Push-Pull Output Clock Driver Oppclk 11 Push-Pull Output Driver OPPAC Characteristics AC CharacteristicsAC Test Conditions TSU TDH 13 AC SpecificationsTSU1 TDH2 AC Characteristics Page Ambient temperature requirement Operating TemperatureOperating Temperature at Heat Sink Center Tc Thermal ManagementΘca at Various Airflows for 21264/EV67 Operating Temperature10-2Thermal Management Heat Sink Specifications Heat Sink Specifications10-4Thermal Management Type 1 Heat SinkType 2 Heat Sink 10-6Thermal Management Type 3 Heat SinkThermal Design Considerations Thermal Design ConsiderationsPage Test Pins Testability and DiagnosticsDedicated Test Port Pins Testability and DiagnosticsSROM/Serial Diagnostic Terminal Port SROM/Serial Diagnostic Terminal Port11-2Testability and Diagnostics Srom Load OperationIeee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin Power-Up Self-Test and Initialization Power-Up Self-Test and InitializationBuilt-in Self-Test Srom InitializationSerial Instruction Cache Load Operation 11-6Testability and DiagnosticsIcache Bit Fields in an Srom Line See Appendix B for a listing of the Boundary-Scan RegisterReferences Page Alpha Instruction Summary Alpha Instruction SetTable A-1 Instruction Format and Opcode Notation Alpha Instruction Set A-1Alpha Instruction Summary Pcd Trap to PALcode Mbr Branch to subroutineOpr 11.24 Cmove if = zero Opr 11.46 Cmove if ≥ zero17.010 Convert longword to quadword 15.0AF Convert Gfloating to quadword15.0BC Convert quadword to Ffloating 15.0BE Convert quadword to Gfloating17.02E Fcmove if ≤ zero 17.02F Fcmove if zero17.02C Fcmove if zero 17.02B Fcmove if ≠ zeroOpr 13.60 Multiply quadword with integer overflow enable Opr 13.40 Multiply longword with integer overflow enableOpr 1C.31 Pixel error Mem Load SfloatingMbr 1A.2 Return from subroutine Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 10.02 Scaled add longword byReserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point Instructions Independent Floating-Point Instructions VAX Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode SummaryMem Res Mem Table A-9explains the symbols used in Table A-8Ieee floating-point instruction opcodes Floating-point operate instruction opcodesIeee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Alpha Instruction Set A-15 Table A-11 Exceptional Input and Output ConditionsCmptlt Cmptle Input Cmpteq Cmptun Input16Alpha Instruction Set Alpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys CpysnPage Boundary-Scan Register 21264/EV67 Boundary-Scan RegisterPllvdd Boundary-Scan Register21264/EV67 Boundary-Scan Register B-3 421264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-5 621264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-7 821264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-9 1021264/EV67 Boundary-Scan Register 21264/EV67 Boundary-Scan Register B-11 1221264/EV67 Boundary-Scan Register Serial Icache Load Predecode Values C-1 Serial Icache Load Predecode ValuesPage PALcode Restrictions and Guidelines D-1 PALcode Restrictions and Guidelines2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines Initwritemany PALcode Restrictions and Guidelines D-56PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-9 Restriction 7 Replay Trap, Interrupt Code Sequence, and STFRestriction 9 PALmode Istream Address Ranges Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and GuidelinesRestriction 11 Ibox IPR Update Synchronization Restriction 11 Ibox IPR Update SynchronizationRestriction 13 DTB Fill Flow Collision Restriction 14 HwretGuideline 16 JSR-BAD VA Guideline 20 Ictlsbe Stream Buffer EnableRestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 16 JSR-BAD VARestriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Guideline 26 Conditional Branches in PALcode Restriction 25 Hwmtpr Itbia After ResetRestriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm 14PALcode Restrictions and GuidelinesRestriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodePALcode Restrictions and Guidelines D-15 16PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRRestriction 32 Pctrctl Update Restriction 31 ICTLVA48 UpdateRestriction 31 ICTLVA48 Update PALcode Restrictions and Guidelines D-17Restriction 33 Hwld Physical/Lock Use Guideline 35 Hwintclr UpdateRestriction 36 Updating Ictlsde Restriction 37 Updating VACTLVA48PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error20PALcode Restrictions and Guidelines Restriction 40 Scrubbing a Single-Bit ErrorRestriction 43 No Trappable Instructions Along with Restriction 42 Updating VACTL, CCCTL, or CC IPRsPALcode Restrictions and Guidelines D-21 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache ErrorsPALcode Restrictions and Guidelines D-23 Restriction 47 Cache Eviction for Single-Bit Cache Errors24PALcode Restrictions and Guidelines Forwarding Clock Pin Groupings 21264/EV67-to-Bcache Pin InterconnectionsTable E-1 Bcache Forwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs Late-Write Non-Bursting SSRAMsData Pin Usage Tag Pin UsageDual-Data Rate SSRAMs Dual-Data Rate SSRAMsData and Tag Pin Usage Table E-4 Dual-Data Rate Ssram Data Pin UsageTable E-5 Dual-Data Rate Ssram Tag Pin Usage TrstlGlossary BIU BSR Cisc CPI CmosCPU CSRDram DMADTB DTLFET FepromFEU FpgaIDU GclkIpga IowbITB JfetMBO MAFMBZ MipsNaturally Aligned MSINmos NvramPGA PALPLA PlccProm PqfpRAM RASROM RiscRTL SAMSimm SdramSIP SippTTL StramUart UnalignedUvprom UnpredictableVAF VDFWriteblock WARNumerics IndexIndex-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12